Transmit Fifo Level (Tfl); Receive Fifo Level (Rfl) - Intel IXP45X Developer's Manual

Synchronous Serial Port—Intel
the ROR bit is asserted, and the newly received data is discarded. This process is
repeated for each new piece of data received until at least one empty FIFO entry exists.
When the ROR bit is set, an interrupt request is made. Writing 1 to this bit resets ROR
status and its interrupt request.
After this ROR interrupt occurs, it is recommended that the user read the receive FIFO
to empty it, then clear the ROR bit.
20.5.3.7

Transmit FIFO Level (TFL)

This 4-bit value shows how many valid entries are currently in the Transmit FIFO.See
register table below for details.
20.5.3.8

Receive FIFO Level (RFL)

This 4-bit value shows how many valid entries are currently in the Receive FIFO. See
register table below for details.
The following bit table shows the bit locations corresponding to the status and flag bits
within the SSP status register. All bits are read-only except ROR, which is read/write.
Writes to TNF, RNE, BSY, TFS, and RFS have no effect. Note that writes to reserved bits
are ignored and reads to those bits return zeros.
Register Name:
Block
0xC801_20
Base Address:
SSP Status Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
Register
Bits Name
31:16 (Reserved) (Reserved)
Receive FIFO Level:
Number of entries minus one in Receive FIFO.
15:12 RFL
Note:
Transmit FIFO Level:
Number of entries in Transmit FIFO.
11:08 TFL
Note:
Receive FIFO Overrun:
7 ROR
0 = Receive FIFO has not experienced an overrun
1 = Attempted data write to full Receive FIFO, request interrupt
Receive FIFO Service Request:
0 = Receive FIFO level is below RFT threshold, or SSP disabled.
6 RFS
1 = Receive FIFO level is at or above RFL threshold, request
Transmit FIFO Service Request:
0 - Transmit FIFO level exceeds TFT threshold, or SSP disabled
5 TFS
1 - Transmit FIFO level is at or below TFL threshold, request
interrupt
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Offset Address
Description
When the value 0xF is read, the FIFO is either empty or
full and the programmer should refer to the RNE bit.
When the value 0x0 is read, the FIFO is either empty or
full and the programmer should refer to the TNF bit.
interrupt
SSSR
0x08
RFL TFL
SSSR (Sheet 1 of 2)
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
0x0000_0000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
Rsvd.
Reset Value Access
0x0000 RV
0000 RO
0000 RO
0 RW
0 RO
0 RO
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