Time Sync Control Register - Intel IXP45X Developer's Manual

Time Synchronization Hardware Assist (TSYNC)—Intel
Line of Network Processors
19.5.2.1

Time Sync Control Register

Register Name:
Block
RegBlockAddress
Base Address:
Time Sync Control Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
31:4 (Reserved) Reserved for future use.
AMMS Interrupt Mask. Controls whether the Auxiliary Master Mode
snapshot indication, which is the snm bit in the Time Sync Event register,
should interrupt the Host processor.
3 amm
• When this bit is set, the interrupt to the Host is enabled.
• When cleared, the AMMS interrupt to the Host is disabled.
ASMS Interrupt Mask. Controls whether the indication that an Auxiliary
Slave Mode snapshot, which is the sns bit in the Time Sync Event register, has
been taken should interrupt the Host processor.
2 asm
• When this bit is set, the interrupt to the Host is enabled.
• When cleared, the ASMS interrupt to the Host is disabled.
Target Time Interrupt Mask. Controls whether the Target Time interrupt is
passed to the Host processor.
1 ttm
• When this bit is set, the interrupt to the Host is enabled.
• When cleared, the Target Time interrupt to the Host is disabled.
Reset.
• When a '1' is written to this bit, all logic is returned to the same default
0 rst
• After writing a '1' to this bit to reset the logic, the firmware must write a
August 2006
Order Number: 306262-004US
Offset Address
(Reserved)
Description
state as when a power-on reset occurs.
'0' to the bit to indicate the end of the reset.
® ®
IXP45X and Intel IXP46X Product
TS_Control
0x000
TS_Control
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
x0000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
Reset
Access
Value
x
0
0
0
0
Developer's Manual
0
x
RW
RW
RW
RW
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