Performance Monitoring; Halt: Performance Monitoring Disabled; Cycle Count; Mcu: Dram Transactions - Intel IXP45X Developer's Manual

Performance Monitoring Unit (PMU)—Intel
Processors
Table 255. Duration Events (Sheet 2 of 2)
Observe
d
Interface
MPI
16.3.4

Performance Monitoring

Performance Monitoring consists of a collection of event primitives, which may then be
used for statistical calculations.
Different events on the AHBs are monitored by programming the ESR. Monitoring these
events provide information about the AHB and the AHB initiators.
16.3.4.1

Halt: Performance Monitoring Disabled

Halting one or more counters disables performance monitoring on the halted counter.
In this way any combination or all counters are halted at the same time. Counters are
reset whenever a new mode (not Halt) is selected. Halt/enable is selected on a per
counter basis by the enable bits in the PMR. Halt/enable conditions are maintained in a
separate register from the mux programming because not all of the counter mux
registers can be updated in the same cycle.
The normal expected mode of operation is to halt all counters, program in the counter
event mux selects, and then enable the desired counters.
16.3.4.2

Cycle Count

Selecting mux input 0xFF (event select == 256) simply selects the event 'TRUE' which
has the effect of putting the counter into continuous count mode.
16.3.4.3

MCU: DRAM Transactions

Selecting MCU events enables performance monitoring of the DRAM. All counters are
clocked at the AHB frequency. These transactions are measured using event signals
provided from the DRAM controller. See
information on the semantics of these event signals.
By setting up the IXP45X/IXP46X network processors system-level PMU registers, the
following MCU performance parameters can be monitored:
• Event type 0 : PMU registers ESR0, ESR1 programmed to 0x00000000
PCEC [0-7] contains the page miss counts for each of the 8 possible open pages of
DDR SDRAM.
• Event type 1: PMU registers ESR0, ESR1 programmed to 0x01010101
PCEC [0-7] contains the page hit counts for each of the 8 possible open pages of
DDR SDRAM.
August 2006
Order Number: 306262-004US
®
IXP45X and Intel
Monitored Event
Number of clocks the MPI port is doing
Data Writes.
Name: "MPI[N] Wr Duration"
Number of clocks the MPI port is doing
Data Reads.
Name: "MPI[N] rDDuration"
Number of clocks the MPI port is idle.
Name: "MPI[N] IdleDuration"
Bus acquisition latency for the MPI port.
Name: "MPI[N] Latency Duration"
®
IXP46X Product Line of Network
Increments counter for every cycle MPI port is
transferring write data.
Increments counter for every cycle MPI port is
transferring write data.
Increments counter for every cycle MPI port is not
requesting data nor transferring data.
Increments counter for every cycle MPI port is
requesting a transfer but not acknowledged.
Chapter 11.0, "Memory Controller"
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
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Developer's Manual
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