Back-To-Back 1-Word Inbound Reads With Ex_Slave_Cs_N - Intel IXP45X Developer's Manual

Expansion Bus Controller—Intel
Processors
12.4.5.7

Back-to-Back 1-Word Inbound Reads with EX_SLAVE_CS_N

Figure 156. Back-to-Back 1-Word Inbound Reads with EX_SLAVE_CS_N
- 0 - - 1 -
EX_CLK
EX_ IXPCS _N
EX_ ADDR
ADDR0
EX_RD_N
EX_WR_N
EX_BE_N
EX_ BURST
EX_ WAIT_N
EX_ DATA
EX_ PARITY
STATE
IDLE WAIT
The above timing diagram shows two back-to-back 1-word read data transfers. For
reads, the Expansion bus controller will always assert EX_WAIT_N one cycle after the
assertion of EX_SLAVE_CS_N. As soon as the Expansion bus controller has the data it
will deassert EX_WAIT_N. The deassertion of EX_WAIT_N is dependent on system
activity and could be hundreds of cycles. After the master detects EX_WAIT_N
deasserted, it can deassert EX_SLAVE_CS_N. However, the master can choose to
extend cycle-4 and cycle-12 for as many cycles as it needs. The Expansion bus
controller will continue to drive the read data until the end of the data transfer. In the
second data transfer, the master chose to introduce 2 NOP cycles. The Expansion bus
controller must ignore EX_ADDR during NOP cycles.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel
- 2 - - 3 - - 4 - - 5 -
DATA0
PAR0
DATA0
IXP46X Product Line of Network
- 6 - - 7 - - 8 - - 9 -
ADDR1
IDLE NOP WAIT
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
- 10 - - 11 - - 12 - - 13 -
DATA1
PAR1
DATA1
Developer's Manual
- 14 -
IDLE
B4444-01
695