Ddri Sdram Control Register 1 Sdcr1 - Intel IXP45X Developer's Manual

®
Memory Controller—Intel
11.6.3

DDRI SDRAM Control Register 1 SDCR1

The SDRAM Control Registers (SDCR[1:0]) are responsible for programming the
operation of the DDRI SDRAM state machines as defined in
SDRAM Initialization" on page 598
Programming" on page
parameters required by the DDRI SDRAM state machine not specified in SDCR0.
Note: Each parameter field contains either an IXP45X/IXP46X network processors-required
value limit or an example value derived from a typical device datasheet.
Register Name:
Hex Offset Address:
Register Description:
Access: See below.
31 30 28 27
Register
Bits Name
RESERVED for DDRII. A value of 0
31 (Reserved)
IXP46X network processors.
RTCMD: Read to non-Write Command turnaround period in MCLK
30:2
RTCMD periods. A value of 010
8
network processors.
WTCMD: Write to Command (non-Read) turnaround period in MCLK
periods. This value is computed by using the CAS Latency (t
Write Recovery (t
Vendor specification) using the following equation:
Equation 6. WTCMD = t
27:2
NOTE: t
WTCMD
4
For example, a device specification yields that t
t
WR
7.5ns).
t
WR
Thus, WTCMD = 2.5 + 2 = 4.5, round up to 5 mclks, so a value of
0101
23 (Reserved)
August 2006
Order Number: 306262-004US
®
IXP45X and Intel IXP46X Product Line of Network Processors
602. The SDCR1 specifies the remaining SDRAM timing
DDRI SDRAM Control Register 1 - SDCR1
CC00 E508H
DDRI SDRAM Control Register 1
24 23 22 20 19 17 16
(Rsvd)
DDRI SDRAM Control Register 1 - SDCR1 (External Version) (Sheet 1 of 2)
Description
must be programmed for the IXP45X/IXP46X
2
) measured for the device (provided in the JEDEC/
WR
and t must be converted to mclks for this equation.
CAS WR
is 15ns (and the device speed is 133MHz, so the mclk period is
= (15ns / 7.5ns) = 2 mclks.
should be programmed.
2
and Section 11.2.2.9, "DDRI SDRAM Mode
Reset Hex Value:
12 11
must be used for the IXP45X/
2
CAS
+ t
CAS WR
is 2.5 mclks and
CAS
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Section 11.2.2.8, "DDRI
0x0000 0000H
09 08 04 03 02
R
Default
0
2
000
2
)and
000
2
0
2
Developer's Manual
00
Access
RW
RW
RW
RO
635