Ddri Sdram Initialization Sequence (Controlled With Software) - Intel IXP45X Developer's Manual

®
Memory Controller—Intel
15. The MCU may issue a row-activate command T
command.
16. Software re-enables the refresh counter by setting the RFR to the required value.
The waveform in
Figure 109. DDRI SDRAM Initialization Sequence (Controlled with Software)
(System*)
Command
A11, A12
BA0, BA1
DQ and CB
Notes:
VTT is not applied directly to the device, however t
*
** t
MRD
can be applied.
The two Autorefresh commands may be moved to follow the first MRS, but precede the second Precharge All
command.
If the DDRI SDRAM subsystem implements ECC (see
and Detection"), then initialization software must initialize the entire memory array
with the IXP45X/IXP46X network processors. It is important that every memory
August 2006
Order Number: 306262-004US
®
IXP45X and Intel IXP46X Product Line of Network Processors
Figure 109 illustrates the DDRI SDRAM initialization sequence.
VDD
VDDQ
t
VTD
VTT
VREF
200µs
LVCMOS Low Level
CK
CK_N
t
IS
CKE
t
IS
DM
A0-A9,
A10
High-Z
DQS
High-Z
Power-up:
VDD and CK stable
is required before any command can be applied and 200 cycles of CK are required before a Read command
= Don't Care
cycles after the mode-register-set
mrd
t
CK
t
CH
t t
MRD MRD
t
CL
t
IH
t
IH
NOP PRE EMRS MRS
t
IH
t
IS
CODE CODE
t
t
IH
IH
t t
IS IS
CODE CODE
All Banks
t
IH
t
IS
BA0= BA0=
H L
BA1=L BA1=L
Extended Mode Load Mode
Register Set Register, Reset DLL
must be greater than or equal to zero to avoid device latchup.
VTD
Section 11.2.3, "Error Correction
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
200 cycles of CK**
t t t t
RP RFC RFC MRD
PRE AR AR MRS
CODE
t
IH
t
IS
CODE
All Banks
BA0=
L
BA1=L
Load Mode
Register
(with A8=L)
Developer's Manual
ACT
RA
RA
RA
B2452-02
601