Semaphore Instructions; Coprocessor Instructions; Load And Store Multiple Instruction Timings; Semaphore Instruction Timings - Intel IXP45X Developer's Manual

Intel
Table 89. Load and Store Instruction Timings
Mnemonic
LDRSH
LDRT
PLD
STR
STRB
STRBT
STRD
STRH
STRT
Table 90.

Load and Store Multiple Instruction Timings

Mnemonic
1
LDM
STM
Notes:
1. See
2. numreg is the number of registers in the register list.
3.9.4.8

Semaphore Instructions

Table 91.

Semaphore Instruction Timings

Mnemonic
SWP
SWPB
3.9.4.9

Coprocessor Instructions

Table 92.

CP15 Register Access Instruction Timings

Mnemonic
†
MRC
MCR
† MRC to R15 is unpredictable.
Table 93.

CP14 Register Access Instruction Timings

Mnemonic
MRC
MRC to R15
MCR
LDC
STC
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
188
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
Minimum Issue Latency
1
1
1
1
1
1
2
1
1
Minimum Issue Latency
2 + numreg
2 + numreg
Table 82 on page 184 for LDM timings when R15 is in the register list.
Minimum Issue Latency
5
5
Minimum Issue Latency
4
2
Minimum Issue Latency
8
9
8
11
8
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
5-18 for load data (4 + numreg for last
register in list; 3 + numreg for 2nd to last
2 register in list; 2 + numreg for all other
registers in list);
2+ numreg for write-back of base
2 + numreg for write-back of base
®
Processor
Minimum Result Latency
N/A
1 for writeback of base
1 for writeback of base
1 for writeback of base
2 for write-back of base
1 for writeback of base
1 for writeback of base
Minimum Result Latency
Minimum Result Latency
5
5
Minimum Result Latency
4
N/A
Minimum Result Latency
8
9
N/A
N/A
N/A
August 2006
Order Number: 306262-004US