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25.3
Block Diagram
Figure 206. Exponentiation Acceleration Unit: Block Diagram
Control
Lines
10
Address
In
2
Range
Selects
16
Data
In
Control &
Status
Registers,
Muxes
16
Data
Out
25.3.1
Operand Restrictions
Since the EAU implements modular arithmetic functions using a fixed-size datapath
ALU, there are some assumptions / restrictions for the operands that must be
observed. See
Table 287.
EAU Operand Size Restrictions and Assumptions
Multiplication
Modular Reduction
R = A mod N
Modular Exponentiation
R = M
Modular Inverse
R=A
Note:
k = size of modulus in bits
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
914
®
Intel
IXP45X and Intel
EAU I/F
Control
EAU Register Interface
Table 287
for details.
Operation
Addition
A, B must be same size (k bits)
R = A + B
A, B can be padded with leading zeros out to k bits
Subtraction
A, B must be same size (k bits)
R = A - B
A, B can be padded with leading zeros out to k bits
A, B must be same size (k bits)
R = A * B
A, B can be padded with leading zeros out to k bits
size of A = 2k bits, size of N = k bits
MSB of N = 1, LSB of N can be 0 or 1
Note:
M, e, N must be same size (k bits)
Modulus N is a k-bit number, i.e., 2
MSB & LSB of N = 1
e
mod N
Value of M < N
Note:
A, N must be same size (k bits)
-1
mod N
Value of A < N
®
IXP46X Product Line of Network Processors—Exponentiation
Address
Decode
EAU
Calc
Sequencer
Block
Block
Control
Operand Assumptions
A can be padded with leading zeros.
k-1
e can be padded with leading zeros.
Acceleration Unit
2KB 3-ported RAM
32
32
32
ALU, Shifters, Accumulator,
multiplier, muxes, etc.
EAU Calc Book
B4220-001
Result (R)
Size
k+1 bits
k bits
2k bits
k bits
k
< n < 2
k bits
k bits
August 2006
Order Number: 306262-004US
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