Split Transaction, Interrupt Scheduling Boundary Conditions - Intel IXP45X Developer's Manual

Intel
9.14.12.2.1 Split Transaction Scheduling Mechanisms for Interrupt
Full- and low-speed Interrupt queue heads have an EPS field indicating full- or low-
speed and have a non-zero S-mask field. The host controller can detect this
combination of parameters and assume the endpoint is a periodic endpoint. Low- and
full-speed interrupt queue heads require the use of the split transaction protocol. The
host controller sets the Endpoint Type (ET) field in the split token to indicate the
transaction is an interrupt. These transactions are managed through a transaction
translator's periodic pipeline. Software should not set these fields to indicate the queue
head is an interrupt unless the queue head is used in the periodic schedule.
System software manages the per/transaction translator periodic pipeline by budgeting
and scheduling exactly during which micro-frames the start-splits and complete-splits
for each endpoint will occur. The characteristics of the transaction translator are such
that the high-speed transaction protocol must execute during explicit micro-frames, or
the data or response information in the pipeline is lost.
scheduling boundary conditions that are supported by the EHCI periodic schedule and
queue head data structure. The S and
can schedule start-splits and complete splits, respectively.
Figure 68.

Split Transaction, Interrupt Scheduling Boundary Conditions

The scheduling cases are:
• Case 1: The normal scheduling case is where the entire split transaction is
completely bounded by a frame (H-Frame in this case).
• Case 2a through Case 2c: The USB 2.0 hub pipeline rules states clearly, when and
how many complete-splits must be scheduled to account for earliest to latest
execution on the full/low-speed link. The complete-splits may span the H-Frame
boundary when the start-split is in micro-frame 4 or later. When this occurs, the H-
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IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
Figure 68
C
X labels indicate micro-frames where software
illustrates the general
B4511-01
August 2006
Order Number: 306262-004US