Intel IXP45X Developer's Manual page 20

15.0 GPIO Controller ......................................................................................................776
15.1 Overview ........................................................................................................ 776
15.2 Feature List .................................................................................................... 776
15.3 Block Diagram................................................................................................. 776
15.4 Theory of Operation ......................................................................................... 777
15.4.1 Input Meta-Stability Protection, Edge Detect Logic, Pulse Discrimination....... 778
15.4.2 Clock Generation .................................................................................. 778
15.4.3 APB Interface ....................................................................................... 779
15.5 Detailed Register Descriptions ........................................................................... 779
15.5.1 GPIO Output Register ............................................................................ 779
15.5.2 GPIO Output Enable Register.................................................................. 780
15.5.3 GPIO Input Register .............................................................................. 781
15.5.4 GPIO Interrupt Status Register ............................................................... 781
15.5.5 GPIO Interrupt Type Register 1............................................................... 782
15.5.6 GPIO Interrupt Type Register 2............................................................... 783
15.5.7 GPIO Clock Register .............................................................................. 784
16.0 Performance Monitoring Unit (PMU).......................................................................787
16.1 Overview ........................................................................................................ 787
16.2 Feature List .................................................................................................... 787
16.3 Functional Description ...................................................................................... 787
16.3.1 Programmable Event Counters ............................................................... 788
16.3.2 Occurrence Events ................................................................................ 788
16.3.3 Duration Events.................................................................................... 789
16.3.4 Performance Monitoring ......................................................................... 791
16.3.4.1 Halt: Performance Monitoring Disabled ....................................... 791
16.3.4.2 Cycle Count ............................................................................ 791
16.3.4.3 MCU: DRAM Transactions ......................................................... 791
16.3.4.4 Events ................................................................................... 792
16.4 Previous Master and Slave ................................................................................ 792
16.5 Miscellaneous .................................................................................................. 792
16.5.1 Interrupts ............................................................................................ 792
16.5.2 Reset Conditions................................................................................... 793
16.6 Detailed Register Descriptions ........................................................................... 793
16.6.1 Event Select Registers ........................................................................... 794
16.6.2 PMU Status Register.............................................................................. 795
16.6.3 PMU Mode Register ............................................................................... 795
16.6.4 Programmable Event Counters ............................................................... 796
16.6.5 Previous Master/Slave Register............................................................... 797
16.7 Event Mapping ................................................................................................ 798
17.0 Interrupt Controller................................................................................................803
17.1 Overview ........................................................................................................ 803
17.2 Feature List .................................................................................................... 805
17.3 Block Diagram................................................................................................. 806
17.4 Theory of Operation ......................................................................................... 806
17.4.1 Interrupt Priority .................................................................................. 807
17.4.2 Assigning FIQ or IRQ Interrupts .............................................................. 808
17.4.3 Enabling and Disabling Interrupts ........................................................... 809
17.4.4 Reading Interrupt Status ....................................................................... 809
17.5 Error Enable Register ....................................................................................... 811
17.6 Interrupt Controller Register Descriptions............................................................ 811
17.6.1 Interrupt Status Register ....................................................................... 812
17.6.2 Interrupt Enable Register....................................................................... 813
17.6.3 Interrupt Select Register........................................................................ 813
17.6.4 IRQ Status Register .............................................................................. 814
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
20
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Intel IXP45X and Intel IXP46X Product Line of Network Processors-Contents
August 2006
Order Number: 306262-004US