Supported Ahb Commands - Intel IXP45X Developer's Manual

The EX_IOWAIT_N signal is available to be shared by the devices attached to chip 0
through 7, when the chip selects are configured in Intel or Motorola mode of operation.
The EX_IOWAIT_N signal allows an external device to hold off completion of the read or
write phase of a transaction until the external device is ready to complete the
transaction.
Similarly, EX_RDY_N[3:0] are provided for chip selects 7 through 4, respectively. The
EX_RDY_N[3:0] signals are used to hold off data transfers when chip selects 7 through
4 are configured in HPI mode. For example when chip select 5 is configured in HPI
mode of operation, chip select 5 will no longer respond to the EX_IOWAIT_N signal and
will only respond to the EX_RDY_N[1]. All other chip selects will respond to the
EX_IOWAIT_N signal. Chip selects 7 through 4 are the only chip selects that can be
configured in HPI mode of operation.
As a slave the Expansion bus supports the following AHB commands shown in
Table 218. Commands that are unsupported result in an AHB Error response. For HPI
devices, only half-word read and write transfers are supported in HPI-8 and HPI-16
modes.
Table 218.

Supported AHB Commands

AHB Commands
Single byte read
Single halfword read
Single word read
INCR-4 word read
INCR-8 word read
WRAP-8 word read
Single byte write
Single halfword write
Single word write
INCR-4 write
INCR-8 write
WRAP-8 write
INCR read/write
PCI typically generates
INCR transfers
INCR-16 read/write
WRAP-16 read/write
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
652
® ®
Intel IXP45X and Intel
Supported
Yes
Yes
Yes
Yes
Yes
Yes
Yes, except it is not supported for
Synchronous Intel devices.
Yes
Yes, except it is not supported for
16-bit Synchronous Intel devices
Yes, but only to 32-bit Micron ZBT
devices
Yes, but only to 32-bit Micron ZBT
devices
No
Yes, but only to 32-bit Micron ZBT
devices
No
No
IXP46X Product Line of Network Processors—Expansion Bus
Byte reads to 16-bit devices are only
supported if BYTE_RD16 is set in
EXP_TIMING_CS register
AHB ADDR[0] = '0'
AHB ADDR[1:0] = "00"
AHB ADDR[4:0] <= (less than or equal to)
"10000". Burst will not cross a 8-word
boundary
AHB ADDR[4:0] = "00000"
AHB ADDR[1:0] = "00"
AHB ADDR[0] = '0'
AHB ADDR[1:0] = "00"
AHB ADDR[4:0] <= "10000". Burst will not
cross a 8-word boundary
AHB ADDR[4:0] = "00000"
Burst will not cross a 8-word boundary. For
incr reads, the Expansion bus controller reads
data until the 8-word boundary is reached
before returning the data to the AHB bus.
Controller
Notes/Restrictions
August 2006
Order Number: 306262-004US