Error High Priority Enable Register; Fiq Highest-Priority Register - Intel IXP45X Developer's Manual

Intel
17.6.8

FIQ Highest-Priority Register

Register Name:
0xC800 301C
Physical Address:
This register returns the "incremented number" of the highest-priority interrupt that is
pending for the FIQ. For example, if interrupt '0' is the highest FIQ pending, the register
returns 1.
Register
Description:
Note that the encoded number is shifted left by two bits, a software requirement for the
value to be multiplied by 4 before being read. This allows the register's contents to be
directly used as an offset into a jump table for interrupt vectoring.
Access: Read.
31
Register
Bits Name
31:9 Reserved
8:2 FIQ_ENC_ST
1:0 Reserved
The additional bit defined (i.e. bit 8) of the highest priority register is in the same bit
position as the extended register address. The higher bit of the status can be used as
part of the address calculation to determine which group of registers to access.
17.6.9

Error High Priority Enable Register

Register Name:
0xC800 3034
Physical Address:
This register decides if an interrupt is to be presented to the Intel XScale
Register
priorities. This affects the priority only, not the number reported in the *_ENC_ST registers. Bit 0 of this
Description:
register corresponds to interrupt 32 and bit 31 corresponds to interrupt 63.
Access: Read/Write.
31
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
816
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Interrupt Controller
Reserved
Description
Reserved, Read as undefined, write as 0
Indicates the highest-priority, pending fast interrupt (the interrupt
"number" incremented by 1)
Reserved, Read as undefined, write as 0
Error High Priority Enable[63:32]
INTR_FIQ_ENC_ST
0x00000000
Reset Hex Value:
INTR_FIQ_ENC_ST
ERROR_EN2
0x00000000
Reset Hex Value:
§ §
8 2 1
FRQ_ENC_ST
Reset Value Access
0x000000 RO
0x00 RO
0x0 RO
®
Processor above all other
August 2006
Reference Number: 306262-004US
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