Ldic Cache Functions - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
3.6.14.3

LDIC Cache Functions

The IXP45X/IXP46X network processors support four cache functions that can be
executed through JTAG. Two functions allow an external host to download code into the
main instruction cache or the mini instruction cache through JTAG. Two additional
functions are supported to allow lines to be invalidated in the instruction cache. The
following table shows the cache functions supported through JTAG.
Table 52.

LDIC Cache Functions

Function
Invalidate IC Line
Invalidate Mini IC
Load Main IC
Load Mini IC
RESERVED
Invalidate IC line invalidates the line in the instruction cache containing specified virtual
address. If the line is not in the cache, the operation has no effect. It does not take any
data arguments.
Invalidate Mini IC will invalidate the entire mini instruction cache. It does not effect the
main instruction cache. It does not require a virtual address or any data arguments.
Note: The LDIC Invalidate Mini IC function does not invalidate the BTB (like the CP15
Invalidate IC function) so software must do this manually where appropriate.
Load Main IC and Load Mini IC write one line of data (eight Intel
instructions) into the specified instruction cache at the specified virtual address.
Each cache function is downloaded through JTAG in 33 bit packets.
packet formats for each of the JTAG cache functions. Invalidate IC Line and Invalidate
Mini IC each require 1 packet. Load Main IC and Load Mini IC each require 9 packets.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Encoding
0b000
0b001
0b010
0b011
0b100-0b111
Intel
Arguments
Address
VA of line to invalidate
-
VA of line to load
VA of line to load
-
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
# Data Words
0
0
8
8
-
® *
StrongARM
Figure 23 shows the
Developer's Manual
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