Uart Idd Bit Mapping; Fifo Control Register - Intel IXP45X Developer's Manual

Universal Asynchronous Receiver-Transmitter (UART)—Intel
Product Line of Network Processors
Table 251.

UART IDD Bit Mapping

Interrupt ID Bits
3 2 1 0 Priority
0 0 0 1 -
0 1 1 0 Highest
Second-
0 1 0 0
Highest
Second-
1 1 0 0
Highest
Third-
0 0 1 0
Highest
Fourth-
0 0 0 0
Highest
14.5.7

FIFO Control Register

FCR is a write-only register that is located at the same address as the IIR. (IIR is a
read-only register.) FCR enables/disables the transmitter/receiver FIFOs, clears the
transmitter/receiver FIFOs, and sets the receiver FIFO trigger level.
Register Name:
0xC800 X008
Hex Offset Address:
Register
FIFO Control Register
Description:
Access: Write Only.
31
August 2006
Order Number: 306262-004US
Interrupt SET/RESET Function
Type
None No Interrupt is pending
Overrun Error, Parity Error,
Receiver Line Status
Framing Error, Break Interrupt
Non-FIFO mode: Receive Buffer
is full.
Received Data
Available.
FIFO mode: Trigger level was
reached.
FIFO Mode only: At least 1
Character Time-out character is in receiver FIFO and
indication. there was no activity for a time
period.
Non-FIFO mode: Transmit
Holding Register Empty
Transmit FIFO Data
Request
FIFO mode: Transmit FIFO has
half or less than half data.
Clear-to-Send, Data Set Ready,
Modem Status Ring Indicator, Received Line
Signal Detect
(Reserved)
Intel
® ®
IXP45X and Intel IXP46X
Source
-
Reading the Line Status Register.
Non-FIFO mode: Reading the
Receiver Buffer Register.
FIFO mode: Reading bytes until
Receiver FIFO drops below trigger
level or setting RESETRF bit in FCR
register.
Reading the Receiver FIFO or
setting RESETRF bit in FCR register.
Reading the IIR Register (if the
source of the interrupt) or writing
into the Transmit Holding Register.
Reading the IIR Register (if the
source of the interrupt) or writing
to the Transmitter FIFO.
Reading the Modem Status
Register.
FCR
0x00000000
Reset Hex Value:
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
RESET Control
8 7 6 5 3 2 1
ITL (Rsvd)
Developer's Manual
0
767