Intel IXP45X Developer's Manual page 954

ERR_EN - Control bit for Coprocessor error response enable. This is Bits 14:12 of
configuration register 1 defined in
software global control bit per NPE and NOT per coprocessor. These control bits are
independent of the first three control bits described above in that it dictates the
response of each coprocessor as shown in
zero on reset.
The following scenario describes a typical Error Handling and recovery mechanism. In
all Error Handling scenarios, all three control bits (IPE, DPE, and EEE) must be enabled.
• If there is IMEM, DMEM, or NPE Coprocessor error and the corresponding control bit
is enabled, then the NPE core stops execution. The NPE also asserts an interrupt to
the Intel XScale processor. In addition, the NPE core will indicate to the
Coprocessors that an error happened (NPE error). The error indication to the
coprocessors is sticky and will be deasserted only on resetting the NPE core. There
are two possible scenarios -
— SWCP interrupt is asserted in conjunction with NPE interrupt
— SWCP interrupt is not asserted in conjunction with NPE interrupt
If the SWCP interrupt is asserted in addition to the NPE interrupt, the software must
read the Configuration bus status register (in the NPE core). If the External error status
bit is set and the IMEM or DMEM parity error status bits are not set, the software can
infer a SWCP parity error.
If the SWCP interrupt is not asserted in conjunction with the NPE interrupt, then
potentially there are three causes for the interrupt:
• NPE IMEM Parity error
• NPE DMEM Parity error
• AHB error
The software must read the Configuration bus status register to determine if the error
which occurred is caused by an NPE IMEM Parity error or a NPE DMEM Parity error. If
both the NPE IMEM Parity error and NPE DMEM Parity error bits are not set, then the
interrupt must be a result of an AHB error. The causes of AHB error include:
• AHB Slave access error
• Read/Write to an invalid AHB address access
• An illegal transfer size access on the AHB Bus
The AHB Slave access error can be caused by either an uncorrectable ECC error on
DDRI read access, a parity error on a Queue Manager read Access, a parity error from
an Expansion Bus read access, or an error during a PCI unit access. Refer to the PCI
unit specification for the cause of errors during a PCI unit access. The software can
infer an AHB Slave access error if there is an interrupt from the AHB Slave in addition
to the NPE interrupt. Else, the software can infer an invalid AHB address access or
illegal transfer size access on the AHB.
• Each of the coprocessors behaves uniquely on occurrence of the error. The behavior
of the coprocessors is shown in
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
954
® ®
Intel IXP45X and Intel
Chapter 12, "Expansion Bus Controller."
IXP46X Product Line of Network Processors—Error Handling
Table 299 on page
Table 299 on page 955.
It is a
955. These bits default to
August 2006
Order Number: 306262-004US