Intel IXP45X Developer's Manual page 16

10.5 Register Descriptions........................................................................................ 549
10.5.1 PCI Configuration Registers.................................................................... 549
10.5.2 PCI Configuration Register Descriptions ................................................... 550
10.5.2.1 Device ID/Vendor ID Register ................................................... 550
10.5.2.2 Status Register/Control Register................................................ 551
10.5.2.3 Class Code/Revision ID Register ................................................ 552
10.5.2.4 BIST/Header Type/Latency Timer/Cache Line Register.................. 553
10.5.2.5 Base Address 0 Register........................................................... 553
10.5.2.6 Base Address 1 Register........................................................... 554
10.5.2.7 Base Address 2 Register........................................................... 554
10.5.2.8 Base Address 3 Register........................................................... 555
10.5.2.9 Base Address 4 Register........................................................... 555
10.5.2.10Base Address 5 Register........................................................... 556
10.5.2.11Subsystem ID/Subsystem Vendor ID Register ............................. 556
10.5.2.12Max_Lat, Min_gnt, Interrupt Pin, and Interrupt Line Register......... 557
10.5.2.13Retry Timeout/trdy Timeout Register ......................................... 557
10.5.3 PCI Controller Configuration and Status Registers (CSRs)........................... 558
10.5.3.1 PCI Controller Non-Prefetch Address Register .............................. 559
10.5.3.2 PCI Controller Non-Prefetch Command/Byte Enables Register........ 559
10.5.3.3 PCI Controller Non-Prefetch Write Data Register .......................... 560
10.5.3.4 PCI Controller Non-Prefetch Read Data Register .......................... 560
10.5.3.5 PCI Controller Configuration Port Address/Command/Byte
10.5.3.6 PCI Controller Configuration Port Write Data Register ................... 562
10.5.3.7 PCI Controller Configuration Port Read Data Register ................... 562
10.5.3.8 PCI Controller Control and Status Register .................................. 563
10.5.3.9 PCI Controller Interrupt Status Register ..................................... 564
10.5.3.10PCI Controller Interrupt Enable Register ..................................... 565
10.5.3.11DMA Control Register............................................................... 565
10.5.3.12AHB Memory Base Address Register........................................... 566
10.5.3.13AHB I/O Base Address Register ................................................. 567
10.5.3.14PCI Memory Base Address Register............................................ 567
10.5.3.15AHB Doorbell Register.............................................................. 568
10.5.3.16PCI Doorbell Register ............................................................... 569
10.5.3.17AHB-to-PCI DMA AHB Address Register 0 ................................... 569
10.5.3.18AHB-to-PCI DMA PCI Address Register 0..................................... 570
10.5.3.19AHB-to-PCI DMA Length Register 0 ............................................ 570
10.5.3.20AHB-to-PCI DMA AHB Address Register 1 ................................... 571
10.5.3.21AHB-to-PCI DMA PCI Address Register 1..................................... 571
10.5.3.22AHB-to-PCI DMA Length Register 1 ............................................ 572
10.5.3.23PCI-to-AHB DMA AHB Address Register 0 ................................... 572
10.5.3.24PCI-to-AHB DMA PCI Address Register 0..................................... 573
10.5.3.25PCI-to-AHB DMA Length Register 0 ............................................ 573
10.5.3.26PCI-to-AHB DMA AHB Address Register 1 ................................... 574
10.5.3.27PCI-to-AHB DMA PCI Address Register 1..................................... 574
10.5.3.28PCI-to-AHB DMA Length Register 1 ............................................ 575
10.6 Error/Abnormal Conditions ................................................................................ 575
10.6.1 Error Handling as a PCI Target ............................................................... 575
10.6.2 Error Handling as a PCI Initiator During PCI Direct Access
from the AHB Bus ................................................................................. 577
10.6.3 Error Handling as a PCI Initiator During Non-Prefetch Operations ................ 578
10.6.4 Error Handling During PCI-to-AHB DMA Channel Operations ....................... 578
10.6.5 Error Handling During AHB-to-PCI DMA Channel Operations ....................... 579
11.0 Memory Controller..................................................................................................581
11.1 Overview ........................................................................................................ 581
11.2 Theory of Operation ......................................................................................... 582
11.2.1 Functional Blocks .................................................................................. 582
11.2.1.1 Transaction Ports .................................................................... 584
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
16
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Intel IXP45X and Intel
Enables Register ..................................................................... 561
IXP46X Product Line of Network Processors-Contents
August 2006
Order Number: 306262-004US