Uart Transmit Parity Operation; Uart Receive Parity Operation; Uart Word-Length Select Configuration - Intel IXP45X Developer's Manual

Universal Asynchronous Receiver-Transmitter (UART)—Intel
Product Line of Network Processors
Table 245
Table 245.

UART Transmit Parity Operation

PEN
1
1
1
1
0
Table 246
parity bit.
Table 246.

UART Receive Parity Operation

PEN
1
1
1
1
0
The Stop-Bits Bit (STB) configures the number of stop bits to be transmitted or
received in each serial character. When the Stop-Bits Bit is logic 0, one stop bit is
generated in the transmitted data. When the Stop-Bits Bit is logic 1, and a 5-bit word
length is selected — via the Word Length select bits in the Line Control Register — 1.5
stop bits will be transmitted.
When the Stop-Bits Bit is logic 1 and the word length is selected as a 6, 7, or 8-bit
word, 2 stop bits are transmitted. The UART receiver logic checks the first stop bit only,
regardless of the number of stop bits configured by the Stop Bits bit.
The Word-Length Select (WLS) Bits specify the number of data bits contained in each
transmitted or received serial character. The Word-Length Select Bits configuration is
shown in
Table 247.

UART Word-Length Select Configuration

WLS
Bit 1
0
0
1
1
The Line-Control Register is initialized to hexadecimal 0x00 after reset. The Line-Status
Register is initialized to hexadecimal 0x60 after reset.
August 2006
Order Number: 306262-004US
shows the serial output data configurations for transmission of the parity bit.
Data to be Transmitted
EPS
(Even or Odd Count of 1s to be Transmitted)
0 10101010
0 10101011
1 10101010
1 10101011
X XXXXXXXX
shows the serial input data configurations for reception of data containing a
Data beIng Received + Parity Bit
EPS
(Even or Odd Count of 1s to be Transmitted)
0
0
1
1
X
Table 247.
Number of Data Bits Contained in Each Transmitted Or Received Character
Bit 0
0 5-bit character (default)
1 6-bit character
0 7-bit character
1 8-bit character
®
IXP45X and Intel
101010101
101010110
101010100
101010111
XXXXXXXX
® ®
Intel IXP45X and Intel
®
IXP46X
Value of Parity Bit to be
Transmitted
1
0
0
1
No Parity Bit Sent
Value of Parity Bit Should Be
1
0
0
1
Parity Checking Disabled
IXP46X Product Line of Network Processors
Developer's Manual
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