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Register Name:
0 x C800 B01C
Hex Offset Address:
Register Description: Universal Serial Bus Device Controller Endpoint 3 Control and Status
Register
Description:
Register
Access: Read/Write
31
Bits
31:8
7
6
5
4
3
2
1
0
8.5.6
UDC Endpoint 4 Control/Status Register
The UDC Endpoint 4 control/status register contains six bits that are used to operate
Endpoint 4, an Isochronous OUT endpoint.
8.5.6.1
Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it
and the packet has been error checked by the UDC. A complete packet may be
256 bytes, a short packet, or a zero packet.
UDCCS4[RFS] is not cleared until all data is read from both buffers.
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
302
®
®
Intel
IXP45X and Intel
(Reserved)
Resets (Above)
Register
Name
Reserved for future use.
Transmit short packet (read/write 1 to set).
TSP
1 = Short packet ready for transmission.
(Reserved). Always reads 0.
(Reserved). Always reads 0.
(Reserved). Always reads 0.
Transmit FIFO underrun (read/write 1 to clear).
TUR
1 = Transmit FIFO experienced an underrun.
Flush Tx FIFO (always read 0/ write a 1 to set).
FTF
1 = Flush Contents of TX FIFO.
Transmit packet complete (read/write 1 to clear).
TPC
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
Transmit FIFO service (read-only).
TFS
0 = Transmit FIFO has no room for new data.
1 = Transmit FIFO has room for at least 1 complete data packet.
IXP46X Product Line of Network Processors—USB 1.1 Device
UDCCS3
0 x 00000001
Reset Hex Value:
Bits
UDCCS3
Description
Controller
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
(UDCCS4)
August 2006
Order Number: 306262-004US
0
1
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