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Figure 178. MVIP, Interleaved Mapping of a T1 Frame to an E1 Frame
Note:
In timeslot 0, the frame timeslot is not ignored
Every fourth timeslot received by the HSS is discarded, meaning it is not loaded into
the FIFO and is therefore not sent to the NPE Core.
The HSS can transmit all zeros/ones (NPE Core programmable) for the duration of the
unassigned timeslots.
Received unassigned timeslots are not sent to the NPE Core as they are discarded by
the HSS.
Another method of sending a T1 line over an E1 line called frame mapping is illustrated
in
Figure
timeslots towards the end of the frame. The FBit is located at the last bit of the 32
timeslot, the HSS will not treat this timeslot any differently to other timeslots, it is up
the software to detect the FBit. The NPE Core can select which method it desires to use
when implemented in NPE software.
Figure 179. MVIP, Frame Mapping a T1 Frame to an E1 Frame
2.048
MHz clock
Frame pulse
5
6
7
0
1
Bits
Timeslot
31
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
The NPE Core can program the HSS to automatically ignore (lookup table assigned) the
last eight timeslots. Meaning the NPE Core will not receive the contents of the last eight
timeslots. When timeslot 23 is transmitted, the next data from the NPE Core will not be
transmitted until timeslot zero occurs. The HSS will transmit all zeros/ones for the
duration of the empty timeslots (NPE Core programmable).
The NPE Core must program the HSS to indicate which method of T1 mapping is used
(if any).
13.5.4.2
4.096-Mbps Backplane
This backplane is used to transport two E1s or two T1s on a single line which allows a
clock rate of 4.096 MHz. Two complete E1 frames will fill this frame, therefore
unassigned timeslots are not compulsory. When transporting T1 frames, unassigned
timeslots are used for padding the frame due to the shorter length of the T1 frame.
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
744
®
Intel
IXP45X and Intel
179. This method groups the 24 timeslots together and places unassigned
2
3
4
5
6
FBit
0
1
®
IXP46X Product Line of Network Processors—HSS Coprocessor
2 3
4 5 6 7
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6
nd
0
Unused timeslots
B2450-01
August 2006
Reference Number: 004US
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