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12.4.7
External Expansion Bus Timing Diagram
12.4.7.1
External Arbiter Timing Diagram
Figure 163. External Arbiter Timing Diagram
- 0 -
EX_CLK
EX_CS_N
EXPANSION BUS
OUTPUTS
EX_ GNT0_ IXPREQ _N
EX_ REQ0_ IXPGNT _N
M0_ REQUEST _N
M0_ GRANT _N
STATE
ARBITRATE
The above timing diagram shows the Expansion bus controller requesting the bus in
cycle 0. The external arbiter chooses to grant the Expansion bus controller in cycle 1.
The Expansion bus controller owns the Expansion bus until it deasserts it request in
cycle 4. The Expansion bus controller cannot start a new transfer in cycle 4 or 5 since it
deasserted its request. In cycle 5, the Expansion bus controller asserts request, but
grant is also lost. Since grant was lost in cycle 5, the Expansion bus controller tri-states
the Expansion bus in cycle 6. The arbiter grants the Expansion bus controller in cycle 6
and the Expansion bus controller now owns the bus until it deasserts request in cycle 8.
In cycle 9, the arbiter chose to park the bus on Expansion bus controller, however the
arbiter chose to deassert grant in cycle 10. When bus parking occurs, the Expansion
bus controller cannot start a new transaction until two cycles after its request is
asserted and only if grant remains asserted. If the external arbiter chose to leave grant
asserted to the Expansion bus controller in cycle 10, the Expansion bus controller would
own the bus until it deasserts request again. When Expansion bus controller is parked
on the bus, all shared Expansion bus outputs are driven to the deasserted state.
12.4.8
Configuration Straps
The Expansion bus controller contains configuration registers beyond what is required
for its own configuration. There are several bits of configuration signals provided as
output from the Expansion bus controller to the rest of the IXP45X/IXP46X network
processors. These signals provide the AHB with functions like the software interrupt
capabilities, location of Expansion bus controller in the processor memory map, PCI
Host/Arbiter information, and configuration information on devices connected to the
Expansion Bus.
One of these general-purpose configuration registers is used to capture the value on
the EX_ADDR pins immediately after reset. In the Expansion Bus Interface, 25 address
lines are used to capture this configuration information during reset. When power up is
complete and reset is asserted, the 25 address lines are configured as inputs. When
internal reset is asserted (PLL_LOCK = 0), the configuration registers latch the values
contained on the 25 address lines and the 25 address lines become configured as
outputs. The Expansion Bus address signals have internal pull-up resistors of about
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
700
®
®
Intel
IXP45X and Intel
- 1 -
- 3 -
- 4 -
- 2 -
GNT IXP
ARBITRATE
IXP46X Product Line of Network Processors—Expansion Bus
- 5 -
- 6 -
- 7 -
GNT IXP
Controller
- 8 -
- 9 -
- 10 -
- 11 -
ARBITRATE
GNT M0
B4462-01
August 2006
Order Number: 306262-004US
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