Ssp Control Register 0 (Sscr); Data Size Select (Dss); Frame Format (Frf); External Clock Select (Ecs) - Intel IXP45X Developer's Manual

Intel
Table 274. Register Legend
Attribute
RV
PR
RS
RW
RW1C
20.5.1 SSP Control Register 0 (SSCR0)
The SSP control register 0 (SSCR0) contains five different bit fields that control various
functions within the SSP.
20.5.1.1

Data Size Select (DSS)

The 4-bit data size select (DSS) field is used to select the size of the data transmitted
and received by the SSP. Data can be 4 to 16 bits in length. When data is programmed
to be less than 16 bits, received data is automatically right-justified and the upper bits
in the receive FIFO are zero-filled by receive logic. Transmit data should not be left-
justified by the user before being placed in the transmit FIFO; transmit logic in the SSP
will automatically left-justify the data sample according to the value of DSS before the
sample is transmitted on SSP_TXD. Although it is possible to program data sizes of 1,
2, and 3 bits, these sizes are reserved and produce unpredictable results in the SSP.
When National Microwire frame format is selected, this bit field selects the size of the
received data. Note that the size of the transmitted data is always 8 bits in this mode.
20.5.1.2

Frame Format (FRF)

The 2-bit frame format (FRF) field is used to select which frame format to use: Motorola
SPI (FRF=00), Texas Instruments synchronous serial (FRF=01), or National Microwire
(FRF=10). Note that FRF=11 is reserved and the SSP will produce unpredictable results
if this value is used.
20.5.1.3

External Clock Select (ECS)

The external clock select (ECS) bit selects whether the on-chip 3.6864-MHz clock is
used by the SSP or if an off-chip clock is supplied via SSP_EXTCLK. When ECS=0, the
SSP uses the on-chip 3.6864-MHz clock to produce a range of serial transmission rates
ranging from 7.2 Kbps to a maximum of 1.8432 Mbps. When ECS=1, the SSP uses
SSP_EXTCLK to input a clock supplied from off-chip. The frequency of the off-chip
clock can be any value up to 33.33 MHz. This off-chip clock is useful when a serial
transmission rate, which is not an even multiple of 3.6864 MHz, is required for
synchronization with the target off-chip slave device.
20.5.1.4

Synchronous Serial Port Enable (SSE)

The SSP enable (SSE) bit is used to enable and disable all SSP operations. When
SSE=0, the SSP is disabled; when SSE=1, it is enabled. When the SSP is disabled, all of
its clocks are powered down to minimize power consumption. Note that the SSE is
within the SSP is reset to a known state. It is cleared to zero to ensure the SSP is
disabled following a reset.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
864
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port
Legend
Reserved
Preserved
Read/Set
Read/Write
Normal Read
Write '1' to clear
Attribute Legend
RC Read Clear
RO Read Only
WO Write Only
NA Not Accessible
Normal Read
RW1S
Write '1' to set
August 2006
Order Number: 306262-004US