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Operating System Timer—Intel
18.5.7
Watchdog Enable Register
Register Name:
Physical Address:
Register Description:
Access: Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
31:3
(Reserved)
Count Enable. '1' enables ost_wdog to decrement.
2
wdog_cnt_ena
effect unless ost_wdog_key=0x482E
Interrupt Enable. '1' enables ost_wdog_int signal to be generated.
1
wdog_int_ena
*Only writable when ost_wdog_key=0x482E
Watchdog Reset Enable. '1' enables ost_wdog_reset_n signal to be
0
wdog_rst_ena
generated. *Write has no effect unless ost_wdog_key=0x482E
18.5.8
Watchdog Key Register
Register Name:
Physical Address:
Register Description:
Access: Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
(Reserved)
Register
Bits
Name
31:1
(Reserved)
6
Reset Key Value. Value of the reset key in which access is allowed to
15:0
key_value
ost_wdog_enab and ost_wdog, ost_wdog_key=0x482E
August 2006
Order Number: 306262-004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
0xC8005018
Watchdog Enable Register
(Reserved)
Description
0xC800501C
Watchdog Key Register
Description
Intel
ost_wdog_enab
Reset Hex Value:
ost_wdog_enab
* Write has no
ost_wdog_key
Reset Hex Value:
key_value
ost_wdog_key
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
0x00000000
8
7
6
5
4
3
2
1
Reset
Access
Value
29'd0
RO
0
RW
0
RW
0
RW
0x00000000
8
7
6
5
4
3
2
1
Reset
Access
Value
16'd0
RO
16'd0
RW
Developer's Manual
0
0
825
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