Read N Bytes As A Slave - Intel IXP45X Developer's Manual

I2C Bus Interface Unit—Intel
Read ISR: Slave Address Detected (1), Unit Busy (1), R/nW# bit (1), Ack/Nack (0)
2. Write a 1 to the ISR[Slave Address Detected] bit to clear the interrupt.
3. Return from interrupt.
4. Load data byte to transfer in the IDBR.
5. Write ICR: Set Transfer Byte bit.
6. When a IDBR Transmit Empty interrupt occurs.
Read ISR: IDBR Transmit Empty (1), Ack/Nack (0), R/nW bit (0)
7. Load data byte to transfer in the IDBR.
8. Write ICR: Set Transfer Byte bit.
9. Write a 1 to the ISR[Transmit Empty] to clear interrupt.
10. Wait for interrupt.
Read ISR: Unit Busy (clear), Slave STOP Detected (set).
11. Repeat steps 6 to 10 for n-1 times. If, at any time, the slave does not have data,
the I
12. When a IDBR Transmit Empty interrupt occurs.
Read ISR: IDBR Transmit Empty (1), Ack/Nak(1), R/nW bit (0).
13. Write a 1 to the ISR[Transmit Empty] bit to clear interrupt.
14. Return from interrupt.
15. When Slave Stop Detected interrupt occurs.
Read ISR: Unit Busy(0), Slave STOP Detected(1).
16. Write a 1 to the ISR[Slave Stop Detected] bit to clear interrupt.
21.6.3

Read n Bytes as a Slave

1. When a Slave Address Detected interrupt occurs.
Read ISR: Slave Address Detected(1), Unit busy (1), R/nW bit (0)
2. Write a 1 to the ISR[Slave Address Detected] bit to clear the interrupt.
3. Return from intrerrupt.
4. Write ICR: Set Transfer Byte bit to initiate the transfer
5. When an IDBR Receive Full interrupt occurs.
Read ISR: IDBR Receive Full (1), Ack/Nack (0), R/W# bit (0)
6. Read IDBR: To get the data.
7. Write a 1 to the ISR[Receive Full] bit to clear interrupt.
8. Return form interrupt.
9. Repeat steps 4 to 8 for n-1 times. Once the IDBR is full, the I
low until the data is read.
10. Write ICR: Set Transfer Byte bit to release the I
11. When a Slave Stop Detected interrupt occurs.
Read ISR: Unit busy (0), Slave STOP Detected (1)
12. Write a 1 to the ISR[Slave STOP Detected] bit to clear the interrupt.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
2
C unit keeps SCL low until data is available.
2
C bus and allow next transfer.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
2
C unit will keep SCL
Developer's Manual
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