Asynclistaddr; Endpointlistaddr; Host Controller (Asynclistaddr); Burstsize; Periodiclistbase - Host Controller Frame List Base Address - Intel IXP45X Developer's Manual

Intel
Table 138.

PERIODICLISTBASE - Host Controller Frame List Base Address

Field
BASEADR
(Reserved)
9.12.7

ASYNCLISTADDR; ENDPOINTLISTADDR

Address:
Default Value: 0x00000000
Attribute:
Size:
9.12.7.1

Host Controller (ASYNCLISTADDR)

This 32-bit register contains the address of the next asynchronous queue head to be
executed by the host. Bits [4:0] of this register cannot be modified by the system
software and will always return a zero when read.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Table 139. ASYNCLISTADDR - Host Controller Next Asynchronous Address
Field
ASYBASE[31:5]
(Reserved)
9.12.8

BURSTSIZE

Address:
Default Value: 0x0000_0404
Attribute:
Size:
This register is used to control dynamically change the burst size used during data
movement on the initiator (master) interface.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
(Reserved)
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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® ®
IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
Base Address (Low). These bits correspond to memory address signals [31:12],
respectively.
Only used by the host controller.
Must be written as zeros. During runtime, the values of these bits are undefined.
Base + 158h
Read/Write (Writes must be DWord Writes)
32 bits
ASYBASE[31:5]
Link Pointer Low (LPL). These bits correspond to memory address signals [31:5],
respectively. This field may only reference a Queue Head (OH).
Only used by the host controller.
These bits are reserved and their value has no effect on operation.
Base + 160h
Read/Write (Writes must be DWord Writes)
32 bits
Description
8 7
Description
8 7
TXPBURST
Order Number: 306262-004US
6 5 4 3 2 1 0
(Reserved)
6 5 4 3 2 1 0
RXPBURST
August 2006