Udc Data Register 14 - Intel IXP45X Developer's Manual

Register Name:
0 x C800BC00
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 13 Data Register
Description:
Access: Write
31
Bits
31:8
7:0
8.5.44

UDC Data Register 14

Endpoint 14 is a double-buffered, isochronous OUT endpoint that is 256 bytes deep.
The UDC generates an interrupt request when the EOP is received.
Because it is double-buffered, up to two packets of data may be ready. The data can be
removed from the UDC via a direct read from the Intel XScale processor. If one packet
is being removed and the packet behind it has already been received, the UDC issues a
NAK to the host the next time it sends an OUT packet to Endpoint 14.
This NAK condition remains in place until a full packet space is available in the UDC at
Endpoint 14.
Register Name:
0 x C800BE00
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 14 Data Register
Description:
Access: Read
31
Bits
31:8
7:0
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
350
® ®
Intel IXP45X and Intel
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
DATA Top of endpoint data currently being loaded.
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
DATA Top of endpoint data currently being loaded.
IXP46X Product Line of Network Processors—USB 1.1 Device
UDDR13
0x00000000
Reset Hex Value:
Bits
UDDR13
Description
UDDR14
0x00000000
Reset Hex Value:
Bits
UDDR14
Description
Controller
8 7
(8-Bit Data)
0 0 0 0 0 0 0
(UDDR14)
8 7
(8-Bit Data)
0 0 0 0 0 0 0
August 2006
Order Number: 306262-004US
0
0
0
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