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Register Name:
Physical Address:
Register Description:
Access: Read/Write
3
1
(Reserved)
Register
Bits
Name
31:1
(Reserved)
Not used. Ignored on writes and driven logic '0' on reads.
6
15:1
(Reserved)
Not used.
3
1 = Interrupt pending.
12:0
INT_STAT
0 = No interrupt pending.
15.5.5
GPIO Interrupt Type Register 1
This register describes how to interpret GPIO [7:0] as interrupts, either level or edge,
along with high, low, rising, falling, transitional. Three bits describe each GPIO pin, as
described in the following table. The top [31:24] bits are used to control muxing
between raw data from GPIO_IN[7:0] or GPISR[7:0] to the NPEs.
Register Name:
Physical Address:
Register Description:
Access: Read/Write
3
3
2
2
2
2
2
1
0
9
8
7
6
5
Register
Bits
Name
When '1', a synchronized gpio_in[7] is muxed to gpio_int_npe[7],
31
gpio_npe_7
when '0', gpisr[7] is muxed to gpio_int_npe[7]
30
gpio_npe_6
as per gpio_npe_7
29
gpio_npe_5
as per gpio_npe_7
28
gpio_npe_4
as per gpio_npe_7
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
782
®
Intel
IXP45X and Intel
0xC800400C
This register is used to store status of interrupts received on GP input pins
Description
0xC8004010
This register is used to control interrupt type for GPIO 7:0
2
2
4
3
GPIO7
GPIO6
Description
®
IXP46X Product Line of Network Processors—GPIO Controller
GPISR
Reset Hex Value:
1
1
6
5
GPISR
GPIT1R
Reset Hex Value:
1
1
6
5
GPIO5
GPIO4
GPIO3
GPIT1R (Sheet 1 of 2)
0x00000000
8
7
INT_STAT
Reset
Access
Value
0x0
RO
0x0
RO
0x0000
RW1C
0x00000000
8
7
GPIO2
GPIO1
GPIO0
Reset
Access
Value
0
RW
0
RW
0
RW
0
RW
August 2006
Reference Number: 306262-004US
0
0
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