Modem Status Register - Intel IXP45X Developer's Manual

Intel
Bits
4
3
2
1
0
14.5.11

Modem Status Register

This register provides the current state of the control lines from the modem or data set
(or a peripheral device emulating a modem) to the processor. In addition to this current
state information, four bits of the Modem Status register provide change information.
The 3:0 bits are set to a logic 1 when a control input from the modem changes state.
The bits are reset to a logic 0 when the processor writes ones to the bits of the Modem
Status Register.
Note: When bits 0, 1, 2, or 3 are set to logic 1, a Modem Status Interrupt is generated, if bit
3 of the Interrupt Enable Register is set.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
772
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous
Register
Name
Break Interrupt: BI is set to a logic 1 when the received data input is held in
the spacing (logic 0) state for longer than a full word transmission time (that is,
the total time of Start bit + data bits + parity bit + stop bits). The Break
indicator is reset when the processor reads the Line Status Register.
BI
In FIFO mode, only one character (equal to 00H) is loaded into the FIFO
regardless of the length of the break condition. BI shows the break condition for
the character at the bottom of the FIFO, not the most recently received
character.
Framing Error: FE indicates that the received character did not have a valid
stop bit. FE is set to a logic 1 when the bit following the last data bit or parity bit
is detected as a logic 0 bit (spacing level). The FE indicator is reset when the
processor reads the Line Status Register.
FE The UART will resynchronize after a framing error. To do this, it assumes that
the framing error was due to the next start bit, so it samples this "start" bit
twice and then takes in the "data".
In FIFO mode, FE shows a framing error for the character at the bottom of the
FIFO, not for the most recently received character.
Parity Error: PE indicates that the received data character does not have the
correct even or odd parity, as selected by the even parity select bit. The PE is
set to logic 1 upon detection of a parity error and is reset to logic 0 when the
PE
processor reads the Line Status register. In FIFO mode, PE shows a parity error
for the character at the bottom of the FIFO, not the most recently received
character.
Overrun Error: In non-FIFO mode, OE indicates that the processor did not
read data the receiver buffer register before the next character was received.
The new character is lost. In FIFO mode, OE indicates that all 64 bytes of the
OE
FIFO are full and the most recently received byte has been discarded.
The OE indicator is set to logic 1 upon detection of an overrun condition and
reset when the processor reads the Line Status register.
Data Ready: Bit 0 is set to logic 1 when a complete incoming character has
been received and transferred into the receiver buffer register or the FIFO.
In non-FIFO mode, DR is reset to 0 when the receive buffer is read. In FIFO
mode, DR is reset to a logic 0 if the FIFO is empty (last character has been read
DR
from RBR) or the RESETRF bit is set in the FCR.
0 = No data has been received
1 = Data is available in RBR or the FIFO
Receiver-Transmitter (UART)
LSR
(Sheet 2 of 2)
Description
Order Number: 306262-004US
August 2006