Usb Operation; Signalling Levels; Endpoint Configuration: Universal Serial Bus Device Controller - Intel IXP45X Developer's Manual

Table 107.

Endpoint Configuration: Universal Serial Bus Device Controller

Endpoint Number
Data flow is relative to the USB host. IN packets represent data flow from the UDC to
the USB host. OUT packets represent data flow from the USB host to the UDC.
The FIFOs for the bulk and isochronous endpoints are double-buffered so that one
packet can be processed while the next is being assembled. While the UDC is busy
transmitting an IN packet from a particular endpoint, the Intel XScale processor can be
loading the same endpoint for the next frame transmission. Likewise, while the Intel
XScale processor is unloading an OUT endpoint, the UDC can continue to process the
next incoming packet to that endpoint.
8.3

USB Operation

After an Intel XScale processor reset — or when the USB host issues a USB reset — the
UDC configures all endpoints and is forced to use the USB default address, 0. After the
UDC configures the endpoints, the USB host assigns the UDC a unique address. At this
point, the UDC is under the USB host's control and responds to commands that use
control transactions to transmit to endpoint 0.
The following sections provide details of the USB protocol in a bottom-up fashion,
starting with signalling levels.
8.3.1

Signalling Levels

USB uses differential signalling to encode data and to indicate various bus conditions.
The USB specification refers to the J and K data states to differentiate between high-
and low-speed transmission. Because the UDC supports only 12-Mbps transmission,
references are made only to actual data state 0 and actual data state 1.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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®
Intel IXP45X and Intel
Type
0 Control
1 Bulk
2 Bulk
3 Isochronous
4 Isochronous
5 Interrupt
6 Bulk
7 Bulk
8 Isochronous
9 Isochronous
10 Interrupt
11 Bulk
12 Bulk
13 Isochronous
14 Isochronous
15 Interrupt
®
IXP46X Product Line of Network Processors—USB 1.1 Device
FIFO Size (bytes) X
Function
Number of FIFOs
IN/OUT
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
IN
Controller
16
64x2
64x2
256x2
256x2
8
64x2
64x2
256x2
256x2
8
64x2
64x2
256x2
256x2
8
August 2006
Order Number: 306262-004US