Intel IXP45X Developer's Manual page 28

129 Expansion Bus Write (Intel, Multiplexed Mode) ........................................................... 666
130 Expansion Bus Read (Intel, Multiplexed Mode)............................................................ 667
131 Expansion Bus Write (Intel Simplex-Mode, Synchronous Intel)...................................... 668
132 Expansion Bus Read (Intel Simplex-Mode) ................................................................. 669
133 Intel Synchronous 8-Word Read ............................................................................... 670
134 Intel Synchronous One-Word Read ........................................................................... 671
135 Micron* ZBT Write/Read/Write ................................................................................. 672
136 Micron* ZBT 8-Word Read ....................................................................................... 673
137 Micron* ZBT 4-Word Write....................................................................................... 674
138 Expansion Bus Write (Motorola*, Multiplexed Mode) .................................................... 675
139 Expansion Bus Read (Motorola*, Multiplexed Mode) .................................................... 676
140 Expansion Bus Write (Motorola*, Simplex Mode)......................................................... 677
141 Expansion Bus Read (Motorola*, Simplex Mode) ......................................................... 678
142 Expansion Bus Write (TI* HPI-8 Mode) ...................................................................... 679
143 Expansion Bus Read (TI* HPI-8 Mode) ...................................................................... 679
144 Expansion Bus Write (TI* HPI-16, Multiplexed Mode) .................................................. 680
145 Expansion Bus Read (TI* HPI-16, Multiplexed Mode) ................................................... 680
146 Expansion Bus Write (TI* HPI-16, Simplex Mode) ....................................................... 681
147 Expansion Bus Read (TI* HPI-16, Simplex Mode)........................................................ 681
148 Expansion Bus Inbound State Diagram ...................................................................... 685
149 Multiple IXP45X/IXP46X network processors Connected Back-to-Back............................ 689
150 Back-to-Back 1-Word Inbound Write with EX_SLAVE_CS_N Deasserted ......................... 690
151 Back-to-Back 1-Word Writes without Deasserting EX_SLAVE_CS_N ............................... 691
152 Eight-Word Inbound Write ....................................................................................... 692
153 Eight-Word Inbound Write ....................................................................................... 693
154 Eight-Word Inbound Write with NOPS........................................................................ 693
155 Eight-Word Inbound Write with EX_SLAVE_CS_N Deassertion....................................... 694
156 Back-to-Back 1-Word Inbound Reads with EX_SLAVE_CS_N......................................... 695
157 Back-to-Back 1-Word Reads without EX_SLAVE_CS_N Deasserted ................................ 696
158 Eight-Word Inbound Read........................................................................................ 696
159 Eight-Word Inbound Read with Master Wait States...................................................... 697
160 Eight-Word Inbound Read with Deassertion of EX_SLAVE_CS_N ................................... 698
161 Arbitration When GrantRemove Bit In EXP_MST_CONTROL is Set .................................. 698
162 Arbitration When GrantRemove Bit in EXP_MST_CONTROL is Clear................................ 699
163 External Arbiter Timing Diagram............................................................................... 700
164 Sampling EX_ADDR During Reset ............................................................................. 701
165 Look-Up Table Organization ..................................................................................... 728
166 HSS Core RX Buffer Structure (Identical to TX Buffer Structure) ................................... 729
167 HSS Endianness Examples ....................................................................................... 730
168 TX Frame Sync Example (Presuming Zero Offset) ....................................................... 731
169 FRX Frame Sync Example (Presuming Zero Offset)...................................................... 732
170 T1 TX Frame, HSS Generating Frame Pulse ................................................................ 737
171 T1 TX Frame Using External Frame Pulse ................................................................... 737
172 T1 RX Frame Using External Frame Pulse ................................................................... 738
173 E1 TX Frame, HSS Generating Frame Pulse ................................................................ 739
174 E1 TX Frame, Externally Generated Frame Pulse ......................................................... 739
175 E1 RX Frame, Externally Generated Frame Pulse......................................................... 740
176 GCI Frames, Internally Generated Frame Pulse (Line-Card Mode).................................. 741
177 GCI Frames, Internally Generated Frame Pulse (Termination Mode) .............................. 742
178 MVIP, Interleaved Mapping of a T1 Frame to an E1 Frame............................................ 743
179 MVIP, Frame Mapping a T1 Frame to an E1 Frame ...................................................... 744
180 MVIP, Byte Interlacing Two E1 Streams onto a 4.096-Mbps Backplane ........................... 745
181 MVIP, Byte Interleaving Two T1 Streams onto a 4.096-Mbps Backplane ......................... 746
182 MVIP, Byte Interleaving Four E1 Streams onto a 8.192-Mbps Backplane Bus .................. 746
183 UART Timing Diagram ............................................................................................. 750
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
28
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Intel IXP45X and Intel IXP46X Product Line of Network Processors-Contents
August 2006
Order Number: 306262-004US