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®
Intel XScale
Processor—Intel
Table 40.
TX RX Control Register (TXRXCTRL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
D
reset value: 0x00000000
Bits
31
30
29
28
27:0
3.6.8.1
RX Register Ready Bit (RR)
The debugger and debug handler use the RR bit to synchronize accesses to RX.
Normally, the debugger and debug handler use a handshaking scheme that requires
both sides to poll the RR bit. To support higher download performance for large
amounts of data, a high-speed download handshaking scheme can be used in which
only the debug handler polls the RR bit before accessing the RX register, while the
debugger continuously downloads data.
Table 41
Table 41.
Normal RX Handshaking
Debugger Actions
• Debugger wants to send data to debug handler.
• Before writing new data to the RX register, the debugger polls RR through JTAG until the bit is cleared.
• After the debugger reads a '0' from the RR bit, it scans data into JTAG to write to the RX register and sets
the valid bit. The write to the RX register automatically sets the RR bit.
Debug Handler Actions
• Debug handler is expecting data from the debugger.
• The debug handler polls the RR bit until it is set, indicating data in the RX register is valid.
• Once the RR bit is set, the debug handler reads the new data from the RX register. The read operation
automatically clears the RR bit.
When data is being downloaded by the debugger, part of the normal handshaking can
be bypassed to allow the download rate to be increased.
handshaking used when the debugger is doing a high-speed download. Note that
before the high-speed download can start, both the debugger and debug handler must
be synchronized, such that the debug handler is executing a routine that supports the
high-speed download.
Although it is similar to the normal handshaking, the debugger polling of RR is
bypassed with the assumption that the debug handler can read the previous data from
RX before the debugger can scan in the new data.
August 2006
Order Number: 306262-004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
Access
SW Read-only / Write-ignored
JTAG Write-only
SW Read / Write
SW Read-only/ Write-ignored
JTAG Write-only
SW Read-only/ Write-ignored
JTAG Write-only
Read-as-Zero / Write-ignored
shows the normal handshaking used to access the RX register.
RR
RX Register Ready
OV
RX overflow sticky flag
D
High-speed download flag
TR
TX Register Ready
Reserved
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
8
7
6
5
4
3
Description
Table 42
shows the
Developer's Manual
2
1
0
121
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