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Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.0
Register Set
The registers shown in this section provide access for configuration, alarm monitoring, and control
of the chip.
Table 69 "Optical Module Registers ($ 0x799 - 0x79F)" on page 162
The registers are listed by ascending address in the table.
8.1
Document Structure
The following sections are structured to provide a general overview of the register map. Later
sections provide detailed descriptions of each register segment or bit.
All registers are accessed and addressed as 32-bit doublewords. When accessed using 8- or 16-bit
accesses, the CPU interface packs or unpacks the partial accesses into a 32-bit register value.
8.2
Graphical Representation
Figure 53
represents an overview of the IXF1104 MAC global control status registers that are used
to configure or report on all ports. All register locations shown in
double word.
Figure 53. Memory Overview Diagram
155
Table 59 "MAC Control Registers ($ Port Index + Offset)" on page 156
Global Configuration
Port 3 MAC Control & Statistics
Port 2 MAC Control & Statistics
Port 1 MAC Control & Statistics
Port 0 MAC Control & Statistics
Figure 53
0x7FF
- RX Block Configuration
- TX Block Configuration
0x500
Reserved
0x480
Reserved
0x400
Reserved
0x380
Reserved
0x300
Reserved
0x280
Reserved
0x200
0x180
0x100
0x080
0x000
through
provide register map details.
represent a 32-bit
B0744-01
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
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