Altera cyclone V Technical Reference page 1952

cv_5v4
2016.10.28
Bit
15:0
addrhi
MAC_Address103_Low
The MAC Address103 Low register holds the lower 32 bits of the 104th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
Module Instance
emac0
emac1
Offset:
0xABC
Access:
RW
31 30
15 14
MAC_Address103_Low Fields
Bit
31:0
addrlo
MAC_Address104_High
The MAC Address104 High register holds the upper 16 bits of the 105th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address104 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
Ethernet Media Access Controller
Send Feedback
Name
This field contains the upper 16 bits (47:32) of the
104th 6-byte MAC address.
0xFF700000
0xFF702000
29 28 27 26
13 12 11 10
Name
This field contains the lower 32 bits of the 104th 6-
byte MAC address. The content of this field is
undefined until loaded by software after the initializa‐
tion process.
Description
Base Address
Bit Fields
25 24 23 22
addrlo
RW 0xFFFFFFFF
9 8 7 6
addrlo
RW 0xFFFFFFFF
Description
MAC_Address103_Low
Access
Register Address
0xFF700ABC
0xFF702ABC
21 20 19 18
5 4 3 2
Access
17-737
Reset
RW 0xFFFF
17 16
1 0
Reset
RW 0xFFFFF
FFF
Altera Corporation