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82540EP — Networking Silicon
2.6
Additional Device Features
Four activity and link indication outputs that directly
drive LEDs
Programmable LED functionality
Internal PLL for clock generation can use a 25 MHz
crystal
JTAG (IEEE 1149.1) Test Access Port built in silicon
On-chip power control circuitry
Four software definable pins
Supports little endian byte ordering for both 32 and 64
bit systems and big endian byte ordering for 64 bit
systems
Two or three-pair cable downshift
Provides loopback capabilities
Minimal ballout change from the 82540EM
a. If applying the "low-power" EEPROM setting for the 82540EP chip, then only external voltage regulator circuits should be used
instead of the on-chip power control circuitry
2.7
Technology Features
196-pin Ball Grid Array (TFBGA) package
Pin compatible with 82551QM and 82540EM
controllers
Implemented in 0.15u CMOS process
Operating temperature: 0
operating temperature
Heat sink or forced airflow not required
°
65
C to 140
PCI Signaling: 3.3 V (5 V tolerant) PCI signaling
Typical targeted power dissipation:
•
1.38W @ D0 1000 Mb/s
•
386mW @ D3 100 Mb/s (wake-up enabled)
•
<20mW @ D3 wake-up disabled
8
Features
a
Features
°
°
C to 70
C (maximum)
°
C storage temperature range
Benefits
•
Link and activity indications (10, 100, and 1000
Mbps) on each port
•
Software definable function (speed, link, and
activity) and blinking allowing flexible LED
implementations
•
Lower component count and system cost
•
Simplified testing using boundary scan
•
Reduced number of on-board power supply
regulators
•
Simplified power supply design in less power-
critical applications
•
Additional flexibility for LEDs or other low speed
I/O devices
•
Portable across application architectures
•
Supports modular hardware accessories
•
Validates silicon integrity
•
Pin Compatibility
Benefits
2
•
15 mm
component making LOM designs easier
•
Enables 10/100 Mbps Fast Ethernet or 1000 Mbps
Gigabit Ethernet implementations on the same
board with only minor stuffing option changes
•
Offers lowest geometry to minimize power and
size while maintaining Intel quality reliability
standards
•
Simple thermal design
•
Lower power requirements for mobile applications
Datasheet
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