error in the packet). If, after three attempts, the target function still has not responded, the USB controller flushes
the FIFO and sets the USB_EP[n]_TXCSR_H.TXTOERR bit to interrupt the processor core.
Multi-Point Support
The following sections describe the multi-point support of the USB controller.
•
Allocating Devices to Endpoints
•
Multi-Point Operation
•
Multi-Point Bandwidth Considerations
Allocating Devices to Endpoints
The separate functions of the connected devices are allocated to the endpoints within the USB controller through a
group of three registers. The registers are associated with each implemented Rx or Tx endpoint (including endpoint
0).
The registers are:
• USB_MP[n]_TXFUNCADDR/
• USB_MP[n]_TXHUBADDR/
• USB_MP[n]_TXHUBPORT/
The location of these registers depends on which of the endpoints is being addressed.
Record the address of the target function that is accessed through the selected endpoint in the transmit and receive
function address registers. Record this information separately for each Tx and Rx endpoint used. In particular, set
both
USB_MP[n]_TXFUNCADDR
The USB controller uses the transmit and receive hub address and hub port registers when a full-speed or low-speed
device is connected to it through a high-speed USB 2.0 hub. The hub carries out the required transaction translation
between high-speed transmission and low-speed or full-speed transmission. In this situation, the
USB_MP[n]_TXHUBADDR/
USB_MP[n]_RXHUBPORT
tion. It must also record the address of the port of that hub through which the associated Tx or Rx endpoint must
access the device.
If endpoint 0 is connected to a hub, then set both the Tx and the Rx versions of these registers for this endpoint.
The USB controller also uses hub address registers to record whether the hub offers multiple transaction translators
or just a single transaction translator. This configuration has a significant effect on the overall bandwidth that can be
achieved.
In addition to recording the address of the target function, record the endpoint number and operating speed of the
target device and the type of transaction that is executed. For a Tx endpoint, set this information in the
USB_EP[n]_TXTYPE
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
USB_MP[n]_RXFUNCADDR
USB_MP[n]_RXHUBADDR
USB_MP[n]_RXHUBPORT
and
USB_MP[n]_RXFUNCADDR
USB_MP[n]_RXHUBADDR
registers must record the address of the hub that carries out the transaction transla-
register when the index register is set to select the required endpoint. For an Rx endpoint,
for endpoint 0.
and USB_MP[n]_TXHUBPORT/
Host Mode
27–39
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