Intel IXP28XX Manuals

Manuals and User Guides for Intel IXP28XX. We have 1 Intel IXP28XX manual available for free PDF download: Manual

Intel IXP28XX Manual (154 pages)

Network Processors Hardware Design Guide

Brand: Intel | Category: Computer Hardware | Size: 4.32 MB

Table of Contents
3
Revision History
9
Introduction
11
- System Overview
  11
Product Features of IXP28XX Network Processors
12
- In this Guide
  13
- IXP2800/IXP2850 Network Processor Functional Block Diagram
  13
  - Typographical Conventions
    14
  - Acronyms and Terminology
    14
Guide Conventions
14
- Related Documentation
  16
- Contacting Intel
  16
Power Ratings and Requirements
17
- Power Ratings
  17
Absolute Maximum/Minimum Ratings Table
17
Functional Operating Temperature Range
17
Typical and Maximum Power
18
Functional Operating Voltage Range - 1.4/1.0 Ghz
19
Functional Operating Voltage Range - 650 Mhz
20
Example Power by Supply - 1.4 Ghz
21
Example Power by Supply - 1.0 Ghz
22
Example Power by Supply - 650 Mhz
23
Rdram
33
Qdr Sram
53
- Introduction
  53
- QDR Clocking Scheme
  54
  - SRAM Controller Configurations
    54
Clocking Scheme for a QDR Interface Driving Four Srams
54
SRAM Controller Configurations
55
QDR Address/Rpe/Wpe Mapping
55
Total Memory Per Channel
55
- QDR SRAM Connections
  57
- QDR SRAM Interface
  57
  - Using X9 Versus X18 QDR SRAM Parts
    58
Topologies for Using X9 Versus X18 QDR SRAM Parts
59
- Examples of the QDR Interface
  60
IXP2800 Width-Expanded QDR Interface
60
Ingress IXP28XX Network Processor QDR Modular Channel Depth-Expanded QDR Interface
61
Ingress IXP2800 Network Processor QDR Modular Channel, Four-Load QDR Interface
61
- Signal Groups
  62
- QDR Signal Mapping
  62
An Overview of QDR Signal Groups
62
QDR SRAM Signal Mapping
62
QDR Address Signal Trace Width/Spacing Routing
67
QDR Address Signal Group Routing Guidelines
67
- QDR SRAM D (Data Out) Topology
  68
- D (Data Out) Routing Topology
  68
QDR Address Stack-Up Signal Cross-Section Details
68
QDR D Signal Trace Width/Spacing Routing
69
QDR D Signal Group Routing Guidelines
69
QDR D Stack-Up Signal Cross-Section Details
69
- QDR SRAM Q (Data In) Topology
  70
- Q (Data In) Routing Topology
  70
QDR Q (Data In) Signal Group Routing Guidelines
70
- QDR SRAM K, K# Clock Topologies
  71
QDR Q Stack-Up Signal Cross-Section Details
71
QDR Q Signal Trace Width/Spacing Routing
71
QDR K and K# Signal Group Routing Guidelines
72
- Relationship between Address, Control, Data-OUT and K-Clock
  73
QDR K and K# Routing Topology
72
QDR K-Clock Stack-Up Signal Cross-Section Details
73
- QDR SRAM C, C#, CIN, CIN# Clock Topologies
  74
QDR K and K# Signal Trace Width/Spacing Routing
73
QDR C, C#, CIN, and CIN# Signal Group Routing Guidelines
74
QDR C, C#, CIN, and CIN# Routing Topology
74
QDR C and CIN Clock Signal Trace Width/Spacing Routing Details
75
- QDR SRAM RPE#, WPE#, BWE# Control Topologies
  76
QDR C, C#, CIN, CIN# Signal Trace Width/Spacing Routing
75
QDR Control RPE# and WPE# Signal Group Routing Guidelines
76
QDR Control RPE# and WPE# Signals Routing Topology
76
QDR CONTROL Stack-Up Signal Cross-Section Details
77
QDR Control RPE# and WPE# Signal Trace Width/Spacing Routing
77
QDR Control BWE# Signal Group Routing Guidelines
78
- QDR SRAM VREF Generation
  79
QDR Control BWE# Signals Routing Topology
78
QDR CONTROL Stack-Up Signal Cross-Section Details
79
- Tcam/Sram/Coprocessor Interface
  81
  - Tcam/Sram/Coprocessor Interface - Base Card Side
    81
    
    Interface Topologies
    81
Control BWE# Signal Trace Width/Spacing Routing
79
Tcam/Sram/Coprocessor Interface Guidelines (Address, D, CONTROL, Q, and K-Clocks)
82
Address, D, CONTROL, Q, and K-Clocks Topologies
82
Tcam/Sram/Coprocessor Interface Guidelines (C, C#, CIN, and CIN# Clocks)
83
- IXDP2800 QDR Implementation Guidelines
  84
C, C#, CIN, and CIN# Clocks Topologies
83
Four-QDR SRAM Load Routing Recommendations
85
Example Interconnects on the IXP28XX Network Processor, with a Two-QDRII SRAM Load Per Channel
86
Trace Length from IXP28XX Network Processor to SRAM (C, K, SA, D, and R/W_BW)
87
Trace Length from SRAM to IXP28XX Network Processor (Q Data)
87
- QDR SRAM Alternating Routing Layers
  89
QDR 0 Routing on Layer 13 - Adjacent QDR Clamshell Pairs
89
- IXDP2800 TCAM Implementation
  90
  - TCAM and QDR SRAM Placement
    90
QDR 1 Routing on Layer 12 - Adjacent QDR Clamshell Pairs
90
QDR Signal from IXP28XX Network Processor to Tee Point on Layer 12
93
- QDR SRAM Design Review Checklist
  94
QDR Signal Tee Point Arms Routed on Signal Layers 4 and 13
94
- Package Trace Lengths for QDR Signals
  95
- Package Trace Lengths for QDR Signals
  96
Msf (Spi-4/Csix/Fc)
101
- Media and Switch Fabric Interface
  101
  - Spi-4.2
    101
  - Csix
    102
SPI-4 Clock Configuration for Dual Network Processors
102
- Flow Control Bus
  103
CSIX Flow Control Interfaces: Simplex and Full Duplex Modes
103
- Routing Recommendations for LVDS Signals
  104
LVDS Routing as Signal Pairs
105
- Simulation Results for LVDS Signals on IXDP2800 Advanced Development Platform
  106
Topology 1 Network Length Results
106
Topology 1 - Two Unique Pcbs Connected
106
Topology 2 Network Length Results
107
- Package Trace Lengths for Lvds_Diff Signals
  108
Topology 2 - Two Unique Pcbs with Signal Loopback through Connectors
107
Pci
111
- PCI Controller
  111
- PCI Interface
  111
  - PPCI Bus Interface
    112
    
    PPCI Address/Data Signals
    112
PCI Subsystem
112
- PPCI Clock Signals
  113
PPCI Address/Data Group Guidelines
113
- Address/Data Signals with IDSEL
  114
PPCI Address/Data Signal Topology
113
PPCI Clock Signals Group Guidelines
114
PPCI Clock Signals Topology
114
Address/Data Signals with IDSEL Topology (Showing Only the Ingress Intel® IXP28XX Network Processor)
115
Address/Data Signal with IDSEL Group Guidelines
115
- SPCI Bus Interface
  116
  - SPCI Address/Data Signals
    116
SPCI Address/Data Group Guidelines
116
- SPCI Clock Signals
  117
  - SPCI Clock Signals Topology
    117
  - SPCI Clock Signals Group Guidelines
    117
- SPCI Address/Data Signals with IDSEL
  118
SPCI Address/Data Signal Topology
116
SPCI Address/Data Signals with IDSEL Signal Topology
118
SPCI Address/Data Signals with IDSEL Group Guidelines
119
- Cpci Bus Interface
  120
  - Cpci Signals
    120
Cpci Signal Topology
120
Cpci Signal Group Guidelines
120
- PCI Design Review Checklist
  121
- PCI Routing Examples: IXP2800 Network Processor
  121
IXDP2800 PCI Bus Topology Block Diagram
121
64-Bit PCI Bus Routing between Processors
122
64-Bit PCI Bus Routing from IXP28XX Network Processor to Bridge
123
- Package Trace Lengths for PCI Signals
  124
Generic Slowport Connection
127
- Slowport Interface
  128
Slowport
127
Example Ingress IXP28XX Network Processor Slowport Configuration
128
Example Egress IXP28XX Slowport Configuration
129
CPLD Implementation of a Flash EEPROM Interface
129
- Slowport Signals
  130
  - Topology and Routing
    130
Signal Description
130
Slowport Control Signals Topology
131
Slowport Control Signals Routing Guidelines
131
Slowport Clock Topology
132
Slowport Clock Signals Guideline
132
- Flash Memory and Microprocessor Interface Support
  133
Slowport Address/Data Topology
133
Slowport Address/Data Routing Guidelines
133
- Flash PROM Interface Logic
  134
Slowport Application Topology
135
Mode 0 Single Write Transfer for a Fixed-Timed Device
135
- Microprocessor Interface Logic
  136
Mode 0 Single Write Transfer for a Self-Timing Device
136
An Interface Topology with Intel / AMCC* SONET/SDH Device
139
Mode 3 32-Bit Write Transfer
140
Slowport Mode 3 Write Example Showing TXE +1 Delay Using SP_TXE
141
Mode 32-Bit Read Transfer
142
Slowport Mode 3 Read Example Showing RXE = 2
143
- Summary
  145
Mechanical/Packaging
147
- Package Marking
  147
Intel® IXP2800 Network Processor Package Marking
148
Intel® IXP2850 Network Processor Package Marking
148
- Package Dimensions
  149
Intel® IXP2800 or Intel® IXP2850 Network Processor Package Ball Grid Array
149
Intel® IXP2800 or Intel® IXP2850 Network Processor Package Side View
149
Intel® IXP2800 or IXP2850 Network Processor Package Dimensions
150
- Index
  151
Intel® IXP2800 or Intel® IXP2850 Network Processor Package Top View
150

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