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Texas Instruments TMS320 Series manuals available for free PDF download: User Manual
Texas Instruments TMS320 Series User Manual (288 pages)
DSP/BIOS v5.40
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 2.45 MB
Table of Contents
Table of Contents
7
About DSP/BIOS
17
Chapter 1
18
DSP/BIOS Features and Benefits
18
DSP/BIOS Components
20
DSP/BIOS Modules
21
Configuration Tool Module Tree
23
Naming Conventions
25
DSP/BIOS Standard Data Types
27
Memory Segment Names
28
Standard Memory Segments
29
For more Information
30
Program Generation
31
Chapter 2
32
Creating and Building a Ccsv4 Project for DSP/BIOS Applications
32
Converting Ccsv3.3 Projects to Ccsv4 Projects
40
Configuring DSP/BIOS Applications Statically
41
Methods of Referencing C6000 Global Objects
43
Creating DSP/BIOS Objects Dynamically
46
Files in a DSP/BIOS Application
48
Files Used to Create DSP/BIOS Programs
48
Files Not Included in Rtsbios
52
Using Makefiles to Build Applications
50
Using DSP/BIOS with the Run-Time Support Library
52
Stack Modes on the C5500 Platform
57
DSP/BIOS Startup Sequence
54
Using C++ with DSP/BIOS
58
User Functions Called by DSP/BIOS
61
Calling DSP/BIOS Apis from Main
62
Instrumentation
63
Chapter 3
64
An Overview of Real-Time Analysis
64
Real-Time Analysis Tools in Ccstudio V4.X
65
Runtime Object Viewer (ROV)
72
Instrumentation Performance
77
Examples of Code-Size Increases Due to an Instrumented Kernel
78
Instrumentation Apis
80
LOG Buffer Sequence
82
Target/Host Variable Accumulation
84
Current Value Deltas from Base Value
87
TRC Constants
89
Implicit DSP/BIOS Instrumentation
91
Monitoring Stack Pointers (C5000 Platform)
94
Monitoring Stack Pointers (C6000 Platform)
94
Calculating Used Stack Depth
96
Variables that Can be Monitored with HWI
97
STS Operations and Their Results
98
Instrumentation for Field Testing
100
Real-Time Data Exchange
100
RTDX Data Flow between Host and Target
101
Thread Scheduling
105
Overview of Thread Scheduling
106
Comparison of Thread Characteristics
109
Thread Priorities
111
Thread Preemption
113
Preemption Scenario
114
Hardware Interrupts
115
The Interrupt Sequence in Debug Halt State
119
The Interrupt Sequence in the Run-Time State
121
Software Interrupts
129
Software Interrupt Manager
131
SWI Properties Dialog Box
132
SWI Object Function Differences
135
Using Swi_Inc to Post an SWI
136
Using Swi_Andn to Post an SWI
137
Using Swi_Or to Post an SWI
138
Using Swi_Dec to Post an SWI
139
CPU Registers Saved During Software Interrupt
140
Tasks
143
Execution Mode Variations
146
The Idle Loop
153
Power Management
155
Power Event Notification
161
Semaphores
163
Mailboxes
169
Timers, Interrupts, and the System Clock
175
Interactions between Two Timing Methods
175
Periodic Function Manager (PRD) and the System Clock
180
Memory and Low-Level Functions
183
This Chapter Describes the Low-Level Functions Found in the DSP/BIOS Real- Time Multitasking Kernel. These Functions Are Embodied in the Following Software Modules
183
Allocating Memory Segments of Different Sizes
190
Memory Allocation Trace
193
System Services
194
Queues
197
Input/Output Stream
204
Chapter 6
204
I/O Overview
204
Input/Output Methods
205
Comparing Pipes and Streams
205
Comparing Driver Models
207
Data Pipe Manager (PIP Module)
210
The Two Ends of a Pipe
210
Message Queues
217
Writers and Reader of a Message Queue
217
Components of the MSGQ Architecture
218
MSGQ Function Calling Sequence
219
Transports in a Multi-Processor Example
223
Remote Transport
224
Events on Sending Message to Remote Processor
226
Host Channel Manager (HST Module)
229
I/O Performance Issues
230
Streaming I/O and Device Drivers
231
This Chapter Describes Issues Relating to Writing and Using Device Drivers that Use the Dev_Fxns
231
Chapter 7
232
Overview of Streaming I/O and Device Drivers
232
Device-Independent I/O in DSP/BIOS
232
Generic I/O to Internal Driver Operations
233
Device, Driver, and Stream Relationship
234
Creating and Deleting Streams
235
Stream I/O-Reading and Writing Streams
237
Stackable Devices
246
The Flow of Empty and Full Frames
247
Stackable Devices
247
Controlling Streams
252
Selecting Among Multiple Streams
253
Streaming Data to Multiple Clients
255
Streaming Data between Target and Host
257
Device Driver Template
258
Streaming DEV Structures
260
Device Driver Initialization
263
Opening Devices
264
Flow of DEV_STANDARD Streaming Model
268
Real-Time I/O
268
Placing a Data Buffer to a Stream
269
Retrieving Buffers from a Stream
269
Closing Devices
271
Device Control
273
Device Ready
273
Types of Devices
276
Stacking and Terminating Devices
276
Buffer Flow in a Terminating Device
277
In-Place Stacking Driver
277
Copying Stacking Driver Flow
278
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Texas Instruments TMS320 Series User Manual (88 pages)
DSP Algorithm Standard Rules and Guidelines
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 0.62 MB
Table of Contents
Table of Contents
3
Preface
7
1 Overview
9
Scope of the Standard
10
TMS320 DSP Algorithm Standard Elements
10
Rules and Guidelines
11
Requirements of the Standard
11
Goals of the Standard
12
Intentional Omissions
12
System Architecture
13
Frameworks
13
DSP Software Architecture
13
Algorithms
14
Core Run-Time Support
14
2 General Programming Guidelines
15
Use of C Language
16
Threads and Reentrancy
16
Threads
16
Preemptive Vs. Non-Preemptive Multitasking
17
Reentrancy
17
Example
18
Data Memory
19
Memory Spaces
20
Scratch Versus Persistent
20
Scratch Vs Persistent Memory Allocation
21
Algorithm Versus Application
22
Data Memory Types
22
Program Memory
23
ROM-Ability
23
Use of Peripherals
24
3 Algorithm Component Model
25
Interfaces and Modules
26
Module Interface and Implementation
26
External Identifiers
27
Naming Conventions
28
Module Initialization and Finalization
28
Module Instance Objects
28
Design-Time Object Creation
29
Run-Time Object Creation and Deletion
29
Module Object Creation
29
Example Module Object
29
Module Configuration
30
Example Module
30
Multiple Interface Support
31
Interface Inheritance
32
Summary
32
Algorithms
33
Example Implementation of IALG Interface
33
Packaging
34
Object Code
34
Debug Verses Release
35
Header Files
35
4 Algorithm Performance Characterization
37
Data Memory
38
Heap Memory
38
Stack Memory
39
Static Local and Global Data Memory
39
Program Memory
40
Interrupt Latency
41
Execution Time
41
MIPS Is Not Enough
41
Execution Time Model
42
Execution Timeline for Two Periodic Tasks
42
5 DSP-Specific Guidelines
45
CPU Register Types
46
Register Types
46
Use of Floating Point
47
Tms320C6Xxx Rules and Guidelines
47
Data Models
47
Endian Byte Ordering
47
Program Model
47
Register Conventions
48
Status Register
48
Interrupt Latency
49
Tms320C54Xx Rules and Guidelines
49
Data Models
49
Program Models
49
Register Conventions
51
Status Registers
51
Interrupt Latency
52
Tms320C55X Rules and Guidelines
52
Data Models
52
Stack Architecture
52
Program Models
53
Relocatability
53
Register Conventions
54
Status Bits
55
Tms320C24Xx Guidelines
57
Data Models
57
General
57
Program Models
57
Register Conventions
57
Interrupt Latency
58
Status Registers
58
Tms320C28X Rules and Guidelines
58
Data Models
58
Program Models
59
Register Conventions
59
Status Registers
59
Interrupt Latency
60
6 Use of the DMA Resource
61
Overview
62
Algorithm and Framework
62
Requirements for the Use of the DMA Resource
63
Logical Channel
63
Data Transfer Properties
64
Data Transfer Synchronization
64
Transfer Properties for a 1-D Frame
64
Frame Index and 2-D Transfer of N-1 Frames
64
Abstract Interface
65
Resource Characterization
66
Runtime Apis
67
Strong Ordering of DMA Transfer Requests
67
Submitting DMA Transfer Requests
68
Device Independent DMA Optimization Guideline
68
C6Xxx Specific DMA Rules and Guidelines
69
Cache Coherency Issues for Algorithm Producers
69
C55X Specific DMA Rules and Guidelines
70
Supporting Packed/Burst Mode DMA Transfers
70
Addressing Automatic Endianism Conversion Issues
71
Minimizing Logical Channel Reconfiguration Overhead
71
Inter-Algorithm Synchronization
71
Non-Preemptive System
71
Preemptive System
72
Rules and Guidelines
75
A.1 General Rules
76
General Rules
76
A.3 DMA Rules
77
DMA Rules
77
Performance Characterization Rules
77
A.4 General Guidelines
78
General Guidelines
78
A.5 DMA Guidelines
79
DMA Guidelines
79
Core Run-Time Apis
81
DSP/BIOS Run-Time Support Library
82
TI C-Language Run-Time Support Library
82
C Bibliography
83
Books
83
Urls
83
C.1 Books
83
C.2 Urls
83
D Glossary
85
Glossary of Terms
85
D.1 Glossary of Terms
85
Texas Instruments TMS320 Series User Manual (126 pages)
MPEG4/H263 Decoder on HDVICP2 and Media Controller Based Platform
Brand:
Texas Instruments
| Category:
Media Converter
| Size: 1.53 MB
Table of Contents
Read this First
3
Intended Audience
3
How to Use this Manual
3
Related Documentation from Texas Instruments
4
Related Documentation
5
Text Conventions
7
Product Support
8
Trademarks
8
Table of Contents
9
Contents
11
Figures
11
Tables
13
Introduction
16
Overview of XDAIS, XDM and IRES
16
XDAIS Overview
16
XDM Overview
16
IRES Overview
17
Figure 1-1. IRES Interface Definition and Function Calling Sequence
18
Figure 1-2. Flow Diagram of the MPEG4 Advanced Simple Profile Decoder
20
Supported Services and Features
21
Overview of MPEG4 Advanced Simple Profile Decoder
19
Installation Overview
23
Installing the Component
24
System Requirements
24
Hardware
24
Software
24
Figure 2- 1.Component Directory Structure
25
Before Building the Sample Test Application
29
Installing Framework Component (FC)
29
Installing HDVICP2 and CSP Library
30
Building and Running the Sample Test Application
30
Building the Sample Test Application
30
Running the Sample Test Application on OMAP4 ES1.0
31
Running the Sample Test Application on Dm816X DDR2 EVM REV-B
32
Configuration Files
33
Generic Configuration File
33
Decoder Configuration File
33
Standards Conformance and User-Defined Inputs
35
Uninstalling the Component
35
Sample Usage
37
Figure 3-1. Test Application Sample Implementation
38
Figure 3-2. Process Call with Host Release
41
Algorithm Instance Deletion
42
Frame Buffer Management by Application
42
Frame Buffer Input and Output
42
Frame Buffer Format
43
Frame Buffer Management by Application
43
Overview of the Test Application
38
Algorithm Instance Creation and Initialization
39
Parameter Setup
39
Process Call
40
Figure 3-3. Interaction of Frame Buffers between Application and Framework
43
Figure 3-4. Interaction between Application and Codec
44
Handshaking between Application and Algorithm
44
Address Translations
45
Sample Test Application
46
API Reference
49
Symbolic Constants and Enumerated Data Types
50
Data Structures
60
Common XDM Data Structures
60
MPEG4 Decoder Data Structures
74
Interface Functions
78
Creation Apis
79
Initialization API
81
Control API
82
Data Processing API
84
Termination API
88
Frequently Asked Questions
89
Code Build and Execution
89
Issues with Tools Version
89
Algorithm Related
89
Debug Trace Usage
91
Introduction
91
Enabling and Using Debug Information
91
Debugtracelevel
92
Lastnframestolog
92
Debug Trace Levels
93
Requirements on the Application
93
Picture Format
95
Meta Data Support
103
Error Handling
107
Parse Header Support
113
Support for Display Delay
115
Support for Padding Type
117
Support for Dynamic Change in Resolution
121
Support for Drop of Frame
123
Support for Decoding Only Intra Frames Using Less Memory
125
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Texas Instruments TMS320 Series User Manual (85 pages)
Piccolo Local Interconnect Network LIN Module
Brand:
Texas Instruments
| Category:
Control Unit
| Size: 0.73 MB
Table of Contents
Table of Contents
3
Preface
7
Introduction and Features
9
Purpose
9
Features
9
Block Diagram
10
Standards
11
SCI/BLIN Block Diagram
11
Operation
12
Message Frame
12
LIN Protocol Message Frame Format: Master Header and Slave Response
12
Header Fields: Synch Break, Synch, and ID
12
Synchronizer
13
Response Format of LIN Message Frame
13
Response Length with SCIFORMAT(18-16) Programming
13
Baud Rate
14
Header Generation
14
Message Header in Terms of T
15
ID Field
15
Measurements for Synchronization
16
Synchronization Validation Process and Baud Rate Adjustment
17
Extended Frames Handling
18
Optional Embedded Checksum in Response for Extended Frames
18
Timeout Control
19
Checksum Compare and Send for Extended Frames
19
Timeout Values in T
19
Bit Units
19
TXRX Error Detector (TED)
20
TXRX Error Detector
21
Classic Checkbyte Generation at Transmitting Node
22
LIN 2.0-Compliant Checkbyte Generation at Transmitting Node
22
Message Filtering and Validation
23
ID Reception, Filtering and Validation
23
Receive Buffers
24
2.10 Transmit Buffers
25
Receive Buffers
25
Interrupts
26
Transmit Buffers
26
General Interrupt Scheme
27
SCI/BLIN Interrupts
27
Low-Power Mode
28
Interrupt Generation for Given Flags
28
LIN Message Frame Showing LIN Interrupt Timing and Sequence
28
Entering Sleep Mode
29
Wakeup
29
Wakeup Timeouts
30
Emulation Mode
30
Wakeup Signal Generation
30
SCI/BLIN Control Registers
31
LIN Registers
31
SCI Global Control Register 0 (SCIGCR0)
32
SCI Global Control Register (SCIGCR1)
32
SCI Global Control Register (SCIGCR2)
32
SCI Set Interrupt Register (SCISETINT)
32
SCI Clear Interrupt Register (SCICLEARINT)
33
SCI Set Interrupt Level Register (SCISETINTLVL)
33
SCI Clear Interrupt Level Register (SCICLEARINTLVL)
34
SCI Flags Register (SCIFLR)
34
SCI Interrupt Vector Offset 0 (SCIINTVECT0)
34
SCI Interrupt Vector Offset 1 (SCIINTVECT1)
34
SCI Format Control Register (SCIFORMAT)
35
Baud Rate Selection Register (BRSR)
35
Transmit Data Buffer Register (SCITD)
35
LIN Mask Register (LINMASK)
36
SCI Pin I/O Control Register 2 (SCIPIO2)
36
LIN Compare Register (LINCOMPARE)
36
LIN Receive Buffer 0 Register (LINRD0)
36
LIN Receive Buffer 1 Register (LINRD1)
36
LIN Identification Register (LINID)
37
LIN Transmit Buffer 0 Register (LINTD0)
37
LIN Transmit Buffer 1 Register (LINTD1)
37
Maximum Baud Rate Selection Register (MBRS)
37
I/O Design for Test Control (IODFTCTRL) Register
38
SCI Global Control Register 0 (SCIGCR0)
39
SCI Global Control Register (SCIGCR1)
39
SCI Global Control Register 0 (SCIGCR0) Field Descriptions
39
SCI Global Control Register (SCIGCR1) Field Descriptions
40
Bit
44
SCI Global Control Register (SCIGCR2)
44
SCI Receiver Status Flags
44
SCI Transmitter Status Flags
44
SCI Global Control Register (SCIGCR2) Field Descriptions
44
SCI Set Interrupt Register (SCISETINT)
46
SCI Set Interrupt Register (SCISETINT) Field Descriptions
46
SCI Clear Interrupt Register (SCICLEARINT)
50
SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions
50
SCI Set Interrupt Level Register (SCISETINTLVL)
54
SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions
54
SCI Clear Interrupt Level Register (SCICLEARINTLVL)
57
SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions
57
SCI Flags Register (SCIFLR)
61
SCI Flags Register (SCIFLR) Field Descriptions
61
SCI Interrupt Vector Offset 0 (SCIINTVECT0)
67
SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions
67
SCI Interrupt Vector Offset 1 (SCIINTVECT1)
68
SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions
68
SCI Format Control Register (SCIFORMAT) Field Descriptions
68
Baud Rate Selection Register (BRSR)
69
Receiver Emulation Data Buffer (SCIED)
70
Baud Rate Selection Register (BRSR) Field Descriptions
70
SCI Data Buffers (SCIED, SCIRD, SCITD)
70
Receiver Data Buffer (SCIRD)
71
Receiver Emulation Data Buffer (SCIED) Field Descriptions
71
Receiver Data Buffer (SCIRD) Field Descriptions
71
Transmit Data Buffer Register (SCITD) Field Descriptions
72
SCI Pin I/O Control Register 2 (SCIPIO2) Field Descriptions
72
LIN Compare Register (LINCOMPARE) Field Descriptions
73
LIN Receive Buffer 0 Register (LINRD0) Field Descriptions
74
LIN Receive Buffer 1 Register (LINRD1) Field Descriptions
75
LIN Mask Register (LINMASK) Field Descriptions
75
LIN Identification Register (LINID) Field Descriptions
76
LIN Transmit Buffer 0 Register (LINTD0) Field Descriptions
77
LIN Transmit Buffer 1 Register (LINTD1) Field Descriptions
77
6.23 I/O Design for Test Control (IODFTCTRL) Register
78
Maximum Baud Rate Selection Register (MBRS) Field Descriptions
78
I/O Design for Test Control (IODFTCTRL) Register Field Descriptions
79
BLIN SCI Vs. Standard SCI
81
SCI Vs. LIN-SCI Programming
81
Appendix A Revision History
84
Revision a Changes
84
Texas Instruments TMS320 Series User Manual (70 pages)
SECOND GENERATION DIGITAL SIGNAL PROCESSORS
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 0.55 MB
Table of Contents
Instruction Set
10
Addressing Modes
10
Repeat Feature
10
Instruction Set Summary
11
Development Support
18
Documentation Support
20
Specification Overview
20
Recommended Operating Conditions
21
Hold Timing
25
Eprom Programming
33
Timing Diagrams
41
Clock Timing
41
Memory Read Timing
42
Memory Write Timing
43
Reset Timing
45
Mechanical Data
55
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