Texas Instruments OMAP5912 Reference Manual page 1500

Multimedia processor device overview and architecture
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USB OTG Controller
Table 64. OTG System Configuration Register 2 (OTG_SYSCON_2) (Continued)
Bit
Name
7
HMC_TLLSPEED
6
HMC_TLLATTACH
5:0
HMC_MODE
† See Table 65, OTG_PADEN Source Status.
‡ See Table 66, HMC_PADEN: USB Signal Multiplexing Control Source.
208
Universal Serial Bus (USB)
Description
The HMC TLL SPEED configuration bit controls the way that the
OMAP5912 transceiverless link logic models the speed of the
transceiverless link when HMC_PADEN is 0. When HMC_PADEN is 1, this
bit has no effect on the transceiverless link logic and writes to this bit have
no effect.
0: Transceiverless link logic models a low-speed (1.5M bits-per-second)
USB link.
1: Transceiverless link logic models a full-speed (12M bits-per-second)
USB link.
This register is cleared 0 by soft reset or hardware reset.
Proper operation of the transceiverless link logic requires that the USB host
controller is clocked when the transceiverless link logic is used, even if the
transceiverless link logic is not connected to a USB host controller port.
The HMC TLL ATTACH configuration bit controls the OMAP5912
transceiverless link logic attach/detach status when HMC_PADEN is 0.
When HMC_PADEN is 1, this bit has no effect on the transceiverless link
logic and writes to this bit have no effect.
0: Transceiverless link logic models a detached link.
1: Transceiverless link logic models an attached link.
This register is cleared 0 by soft reset or hardware reset.
Proper operation of the transceiverless link logic requires that the USB host
controller is clocked when the transceiverless link logic is used, even if the
transceiverless link logic is not connected to a USB host controller port.
The HMC mode configuration bits control the OMAP USB signal
multiplexing selection when HMC_PADEN is 0. When HMC_PADEN is 1
this field is unused and writes to this register have no effect.
HMC_MODE values are discussed in Section 4.3, Pin Multiplexing.
This register is cleared 0x0 by soft reset or hardware reset.
This read-write register provides control and status for various aspects of OTG
controller, USB pin multiplexing, and USB host controller functionality.
SPRU761A

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