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USB OTG Controller
4.2.2
OTG Controller Power Management
224
Universal Serial Bus (USB)
and OTG_CTRL can be accessed when the 48-MHz clock input is inactive.
Accesses to OTG_SYSCON_2 and OTG_CTRL require that the OTG
controller 48-MHz clock be active.
The OTG controller 48-MHz clock must be enabled at both the ULPD level and
the OTG module level whenever USB On-The-Go functionality is needed. It
is not appropriate to disable the OTG controller 48-MHz clock when a USB
On-The-Go link is established with another USB On-The-Go dual-role device.
The OTG controller uses the same 48-MHz clock input from the ULPD module
to provide clocks to the USB device controller and the USB host controller.
When the ULPD 48-MHz clock to the OTG module is disabled, the USB host
controller registers cannot be accessed and the USB host controller cannot
respond to any downstream USB bus activity.
The OTG module can disable the USB device controller clock using
OTG_SYSCON_1.DEV_IDLE_EN. When the ULPD 48-MHz clock to the OTG
module is disabled, or when OTG_SYSCON_1.DEV_IDLE_EN is 1, the USB
device controller registers cannot be accessed, but the USB device controller
can respond to USB bus resume signaling by issuing a USB device controller
general interrupt. System software can read USB device controller registers
when OTG_SYSCON_1.DEV_IDLE_EN is 1, but must enable the 48-MHz
clock to the USB device controller before writing to the USB device controller
registers.
Hardware reset of the USB OTG module is provided by the ULPD module. The
PER_EN bit in the MPU reset control 2 register controls the reset to many
OMAP5912 peripherals, including the USB OTG module. When held in
hardware reset, the USB OTG controller cannot perform USB On-The-Go
SRP or HNP protocols, and its registers cannot be accessed.
The
OTG
controller
OTG_SYSCON_1.SOFT_RESET is written with a 1, the OTG controller, the
USB device controller, and the USB host controller are reset. Soft reset is
complete
when
OTG_SYSCON_1.SOFT_RESET automatically clears itself.
OTG
controller
power
OTG_SYSCON_2.OTG_EN bit. When OTG_SYSCON_2.OTG_EN is 0, OTG
controller power consumption is reduced, because the OTG controller logic is
not clocked. The OTG controller cannot perform On-The-Go HNP or SRP
when it is not clocked.
provides
a
soft
reset
OTG_SYSCON_1.RESET_DONE
management
is
mechanism.
When
is
provided
using
the
SPRU761A
1.
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