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USB Device Controller
Non-Isochronous IN (MPU −> USB HOST) DMA Transactions
186
Universal Serial Bus (USB)
Non-ISO (bulk) TX DMA file transfers are virtually unlimited in size. The
flowcharts depicted in Figure 43 and Figure 44 show how to handle small,
medium, or large file transfers.
TXDMA0, TXDMA1, and TXDMA2 registers operate for non-ISO endpoints in
the following manner. The transfer size counter (TXDMAn.TXN_TSC)
corresponds to either the number of bytes to transmit (EOT bit set) or the
number of buffers to transmit (EOT bit cleared). The buffer size corresponds
to the programmed size of the TX endpoint.
A request to the MPU main DMA controller is generated when the endpoint
buffer is empty initially after that the START bit is set and then each time there
is space free in TX FIFO for other TX packet to be written, until
TXDMAn.TXn_TSC counts down to zero. The request is removed when the
buffer is full or when there are no more bytes of data to be sent.
A DMA transmit transfer done interrupt is signaled to the MPU after the last IN
transaction completes successfully. This is after START bit was set and after
TXDMAn.TXn_TSC equals 0 for the selected DMA channel.
The MPU must not initiate a new TX DMA transfer until it receives a TX_DONE
interrupt.
A small file transfer less than 1024 bytes can be achieved in a single pass DMA
signaled by a single interrupt completion. A file size equal to or greater than
1024 bytes needs two or more DMA passes, signaled by an interrupt
completion after each pass.
Figure 43 shows the necessary steps to prepare and permit a TX DMA transfer
of any size. It also effectively starts the initial DMA transfer. The completion of
this DMA task is signaled to the MPU via a DONE interrupt, whose handler is
shown in Figure 44. The start routine and the associated interrupt handler are
tightly coupled.
SPRU761A
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