Texas Instruments OMAP5912 Reference Manual page 1625

Tables
35 Register Bit Used to Set Receive Frame-Synchronization Polarity
36 Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width
37 Register Bits Used to Set the Receive Clock Mode
38 Receive Clock Signal Source Selection
39 Register Bit Used to Set Receive Clock Polarity
40 Register Bits Used to Set the Sample Rate Generator (SRG) Clock
Divide-Down Value
41 Register Bit Used to Set the SRG Clock Synchronization Mode
42 Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
43 Register Bits Used to Set the SRG Input Clock Polarity
44 Register Bits Used to Place Transmitter in Reset
45 Reset State of Each McBSP Pin
46 Register Bit Used to Set Transmitter Pins to Operate as McBSP Pins
47 Register Bit Used to Enable/Disable the Digital Loopback Mode
48 Receive Signals Connected to Transmit Signals in Digital Loopback Mode
49 Register Bits Used to Enable/Disable the Clock Stop Mode
50 Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
51 Register Bits Used to Enable/Disable Transmit Multichannel Selection
52 Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame
53 Register Bits Used to Set the Transmit Word Length(s)
54 Register Bits Used to Set the Transmit Frame Length
55 How to Calculate Frame Length
56 Register Bit Used to Enable/Disable the Transmit Frame-Synchronization
Ignore Function
57 Register Bits Used to Set the Transmit Companding Mode
58 Register Bits Used to Set the Transmit Data Delay
59 Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode
60 Register Bits Used to Set the Transmit Interrupt Mode
61 Register Bits Used to Set the Transmit Frame-Synchronization Mode
62 How FSXM and FSGM Select the Source of Transmit
Frame-Synchronization Pulses
63 Register Bit Used to Set Transmit Frame-Synchronization Polarity
64 Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width
65 Register Bit Used to Set the Transmit Clock Mode
66 How the CLKXM Bit Selects the Transmit Clock and the Corresponding
Status of the CLKX Pin
67 Register Bit Used to Set Transmit Clock Polarity
68 Register Bits Used to Set Sample Rate Generator (SRG) Clock Divide-Down Value
69 Register Bit Used to Set the SRG Clock Synchronization Mode
70 Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
71 Register Bits Used to Set the SRG Input Clock Polarity
72 Using McBSP Pins for General-Purpose Input/Output
73 McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2
74 Reset State of Each McBSP Pin
75 Pin Control Register Bit Description
14 OMAP5912
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SPRU762B
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156