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SPRU762B
3) The McBSP accepts data bits on the DR pin and shifts them into the
receive shift register(s).
If the word length is 16 bits or smaller, only RSR1 is used. If the word length
is larger than 16 bits, RSR2 and RSR1 are used and RSR2 contains the
most significant bits. For details on choosing a word length, see section
7.8, Set the Receive Word Length(s).
4) When a full word is received, the McBSP copies the contents of the receive
shift register(s) to the receive buffer register(s), provided that RBR1 is not
full with previous data.
If the word length is 16 bits or smaller, only RBR1 is used. If the word length
is larger than 16 bits, RBR2 and RBR1 are used and RBR2 contains the
most significant bits.
5) The McBSP copies the contents of the receive buffer register(s) into the
data receive register(s), provided that DRR1 is not full with previous data.
When DRR1 receives new data, the receiver ready bit (RRDY) is set in
SPCR1. This indicates that receive data is ready to be read by the CPU
or the DMA controller.
If the word length is 16 bits or smaller, only DRR1 is used. If the word length
is larger than 16 bits, DRR2 and DRR1 are used and DRR2 contains the
most significant bits.
If companding is used during the copy (RCOMPAND = 10b or 11b in
RCR2), the 8-bit compressed data in RBR1 is expanded to a left-justified
16-bit value in DRR1. If companding is disabled, the data copied from
RBR[1,2] to DRR[1,2] is justified and bit filled according to the RJUST bits.
6) The CPU or the DMA controller reads the data from the data receive
register(s). When DRR1 is read, RRDY is cleared and the next
RBR-to-DRR copy is initiated.
Note:
If both DRRs are required (word length larger than 16 bits), the CPU or the
DMA controller must read from DRR2 first and then from DRR1. As soon as
DRR1 is read, the next RBR-to-DRR copy is initiated. If DRR2 is not read
first, the data in DRR2 is lost.
When activity is not properly timed, errors can occur. See the following topics
for more details:
Overrun in the Receiver (see section 4.1)
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Unexpected Receive Frame-Synchronization Pulse (see section 4.2)
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Multichannel Buffered Serial Ports (McBSPs)
McBSP Operation
33
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