Texas Instruments OMAP5912 Reference Manual page 1643

McBSP Operation
2.5 McBSP Reception
Figure 12. McBSP Reception Physical Data Path
Á Á Á Á
RSR[1,2] RSR[1,2]
DR
Á Á Á Á
RSR[1,2]: Receive shift registers 1 and 2
RBR[1,2]: Receive buffer registers 1 and 2
Figure 13. McBSP Reception Signal Activity
CLKR
FSR
A1 A0
Á
DR
RRDY
RBR1 to DRR1 copy(A)
CLKR: Internal receive clock
FSR: Internal receive frame-synchronization
signal
32 Multichannel Buffered Serial Ports (McBSPs)
This section explains the fundamental process of reception in the McBSP. For
details about how to program the McBSP receiver, see Receiver Configuration
on page 82.
Figure 12 and Figure 13 show how reception occurs in the McBSP. Figure 12
shows the physical path for the data. Figure 13 is a timing diagram showing
signal activity for one possible reception scenario. A description of the process
follows the figures.
Á Á Á Á
RBR[1,2]
Á Á Á Á
B7 B6 B5 B4
Á
Read from DRR1(A)
The following process describes how data travels from the DR pin to the CPU
or to the DMA controller:
1) The McBSP waits for a receive frame-synchronization pulse on internal
FSR.
2) When the pulse arrives, the McBSP inserts the appropriate data delay that
is selected with the RDATDLY bits of RCR2.
In the preceding timing diagram (Figure 13), a 1-bit data delay is selected.
Á Á Á Á
DRR[1,2] DRR[1,2]
Expand
Á Á Á Á
or
justify and bit fill
DRR[1,2]: Data receive registers 1 and 2
B3 B2 B1 B0
Á
RBR1 to DRR1 copy(B)
DR: Data on DR pin
RRDY: Status of receiver ready bit (high is 1)
To CPU or
DMA controller
C7 C6 C5
Á
Read from DRR1(b)
SPRU762B