Texas Instruments OMAP5912 Reference Manual page 1632

1.3 McBSP Pins
Table 1. McBSP Interface Pins
Pin McBSP1
CLKR
CLKX MCBSP1.CLKX
CLKS MCBSP1.CLKS
DR MCBSP1.DR
SPRU762B
The CPU and the DMA controller communicate with the McBSP through
16-bit-wide registers accessible via the internal peripheral bus. The CPU or
the DMA controller writes the data to be transmitted to the data transmit
registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX via the
transmit shift registers (XSR1, XSR2). Similarly, receive data on the DR pin is
shifted into the receive shift registers (RSR1, RSR2) and copied into the
receive buffer registers (RBR1, RBR2). The contents of the RBRs is then
copied to the DRRs, which can be read by the CPU or the DMA controller. This
allows simultaneous movement of internal and external data communications.
DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted)
if the serial word length is 8 bits, 12 bits, or 16 bits. For larger word lengths,
these registers are needed to hold the most significant bits.
The remaining registers in Figure 2 are registers for controlling McBSP
operation.
Table 1 describes the McBSP interface pins. For information on using these
pins for general-purpose input/output (GPIO), see section 9.
McBSP2 McBSP3
MCBSP2.CLKR
MCBSP2.CLKX MCBSP3.CLKX
MCBSP2.DR MCBSP3.DR
Direction
I/O
I/O
I
I
Multichannel Buffered Serial Ports (McBSPs)
Introduction to McBSPs
Possible Uses
Supplying or reflecting the
receive clock; supplying the
input clock of the sample rate
generator; general-purpose
I/O
Supplying or reflecting the
transmit clock; supplying the
input clock of the sample rate
generator; general-purpose
I/O
Supplying the input clock of
the sample rate generator;
general-purpose input
Receiving serial data; gener-
al-purpose input
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