Texas Instruments OMAP5912 Reference Manual page 1670

4.5.2 Example of Unexpected Transmit Frame-Synchronization Pulse
Figure 32. An Unexpected Frame-Synchronization Pulse During a McBSP
Transmission
CLKX
FSX
A1
DX
XRDY
DXR1 to XSR1 copy(B)
XSYNCERR
SPRU762B
Case 3: Unexpected transmit frame synchronization with XFIG = 0
-
(frame-synchronization pulses not ignored). Unexpected frame-synchro-
nization pulses can originate from an external source or from the internal
sample rate generator.
If a frame-synchronization pulse starts the transfer of a new frame before
the current frame is fully transmitted, this pulse is treated as an unex-
pected frame-synchronization pulse, and the transmitter sets the transmit
frame-synchronization error bit (XSYNCERR) in SPCR2. XSYNCERR
can be cleared only by a transmitter reset or by a write of 0 to this bit.
If you want the McBSP to notify the CPU of frame-synchronization errors,
you can set a special transmit interrupt mode with the XINTM bits of
SPCR2. When XINTM = 11b, the McBSP sends a transmit interrupt
(XINT) request to the CPU each time that XSYNCERR is set.
Figure 32 shows an unexpected transmit frame-synchronization pulse during
normal operation of the serial port with intervals between the data
packets. When the unexpected frame-synchronization pulse occurs, the
XSYNCERR bit is set and the transmission of data B is restarted because no
new data has been passed to XSR1 yet. In addition, if XINTM = 11b, the
McBSP sends a transmit interrupt (XINT) request to the CPU.
A0 B7 B6
Á Á
Write to DXR1(C)
McBSP Exception/Error Conditions
Unexpected frame synchronization
B5 B4 B7 B6 B5 B4
DXR1 to XSR1 (C)
Multichannel Buffered Serial Ports (McBSPs)
B3 B2 B1 B0
Á Á
Write to DXR1(D)
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