Texas Instruments OMAP5912 Reference Manual page 1637

McBSP Operation
Figure 7. Two Methods by Which the McBSP Can Compand Internal Data
RSR1
DR
(2) (DLB)
DX
2.2.3 Reversing Bit Order: Option to Transfer LSB First
2.3 Clocking and Framing Data
2.3.1 Clocking
26 Multichannel Buffered Serial Ports (McBSPs)
The advantage of this method is its speed. The disadvantage is that there
is no synchronization available to the CPU and DMA to control the flow.
DRR1 and DXR1 are internally connected if the (X/R)COMPAND bits are
set to 10b or 11b (compand using µ-law or A-law).
The McBSP is enabled in digital loopback mode with companding
-
appropriately enabled by RCOMPAND and XCOMPAND. Receive and
transmit interrupts (RINT when RINTM = 0 and XINT when XINTM = 0) or
synchronization events (REVT and XEVT) allow synchronization of the
CPU or DMA to these conversions, respectively. Here, the time for this
companding depends on the serial bit rate selected.
RBR1
Expand
(1)
Compress
XSR1
Generally, the McBSP transmits or receives all data with the most significant
bit (MSB) first. However, certain 8-bit data protocols that do not use
companded data require the least significant bit (LSB) to be transferred first.
If you set XCOMPAND = 01b in XCR2, the bit ordering of 8-bit words is
reversed (LSB first) before being sent from the serial port. If you set
RCOMPAND = 01b in RCR2, the bit ordering of 8-bit words is reversed during
reception. Similar to companding, this feature is enabled only if the appropriate
word length bits are set to 0, indicating that 8-bit words are to be transferred
serially. If either phase of the frame does not have an 8-bit word length, the
McBSP assumes the word length is eight bits, and LSB-first ordering is done.
This section explains basic concepts and terminology important for
understanding how McBSP data transfers are timed and delimited.
Data is shifted one bit at a time from the DR pin to the RSR(s) or from the
XSR(s) to the DX pin. The time for each bit transfer is controlled by the rising
or falling edge of a clock signal.
The receive clock signal (CLKR) controls bit transfers from the DR pin to the
RSR(s). The transmit clock signal (CLKX) controls bit transfers from the
XSR(s) to the DX pin. CLKR or CLKX can be derived from a pin at the boundary
of the McBSP or derived from inside the McBSP. The polarities of CLKR and
CLKX are programmable.
DRR1
To CPU or DMA controller
DXR1
From CPU or DMA controller
SPRU762B