Texas Instruments OMAP5912 Reference Manual page 1657

Multimedia processor device overview and architecture

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McBSP Sample Rate Generator

ST-Bus and MVIP Clocking Example

4.096 MHz CLKS

FSR external

Internal FSG, FSR,

Internal FSX

2.048 MHz CLKG,

Internal CLKR,

Internal CLKS

DR, DX (first FSR)

Internal CLKG, CLKR,

(subsequent FSR)

Multichannel Buffered Serial Ports (McBSPs)

For this McBSP configuration:

DLB = 0: Digital loopback mode off, CLKSTP = 00b: Clock stop mode off,

and CLKRM/CLKXM = 1: Internal CLKR/CLKX generated internally by

sample rate generator.

GSYNC = 1: Synchronize CLKG with external frame-synchronization

signal input on FSR pin. CLKG is not synchronized until the

frame-synchronization signal is active. FSR is regenerated internally to

form a minimum pulse width.

SCLKME = 0 and CLKSM = 1: External clock signal at CLKS pin drives

the sample rate generator.

CLKSP = 1: Falling edge of CLKS generates CLKG and thus internal

CLKGDV = 1: Frequency of receive clock (shown as CLKR) is half CLKS

FSRP/FSXP = 1: Active-low frame-synchronization pulse.

RFRLEN1/XFRLEN1 = 11111b: 32 words per frame.

RWDLEN1/XWDLEN1 = 0: 8 bits per word.

RPHASE/XPHASE = 0: Single-phase frame and thus (R/X)FRLEN2 and

(R/X)WDLEN2 are ignored.

RDATDLY/XDATDLY = 0: No data delay.

WxBy = word x bit y

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