Texas Instruments OMAP5912 Reference Manual page 1628

Multichannel Buffered Serial Ports (McBSPs)
1 Introduction to McBSPs
Figure 1. McBSP Area
CompactFlash
Boot ROM
Flash
E
16 M
and
I
SRAM F
S
E
M
16 Memory interface
SDRAM
I
traffic controller (TC)
F
F
O O
C C
P P
− −
T1 T2
Test
RAM
JTAG/
emulation
I/F
SPRU762B
This document describes the three multichannel buffered serial ports
(McBSPs) available on the OMAP5912 device.
The device provides multiple high-speed multichannel buffered serial ports
(McBSPs) that allow direct interface to codecs and other devices in a system.
Figure 1 shows the processor with the McBSP area highlighted.
TMS320C55x DSP
(Instruction cache, SARAM,
32
Endianism
DARAM, DMA,
conversion
H/W accelerators)
DSP
Endianism
MMU
conversion
32
32
interface
32
MPU bus
32
System
DMA
controller
O
C
P
−
I
MPU core
ARM926EJS
32
(Instruction
cache, data
cache, MMU)
LCD
I/F
ETM9
16
Section 1 through section 11 describe McBSP functionality common to all
three McBSPs. Section 12, McBSP in the Device, and section 13, McBSP
Registers, provide specific application information.
DSP
public peripheral bus
16
Level 1/2 interrupt handlers
DSP public (shared)
16
16
MPU
32
32
MPU
peripheral
bridge
32
32
MPU private
peripheral bus
ULPD
Clock and reset management
OSC OSC
Clock Reset External clock
12 MHz 32 kHz
requests
Multichannel Buffered Serial Ports (McBSPs)
DSP public peripherals
DSP private peripherals
McBSP1 (audio PCM I/F)
Timers (3)
Watchdog timer
McBSP3 (optical I/F)
MCSI1 (Bluetooth voice I/F)
MCSI2 (moden voice)
MPU/DSP shared peripherals
Mailbox
peripheral bus
MPU/DSP static shared
8 x GPTIMERS
SPI
UART1, 2, 3
MPU public
2
I C
peripheral bus
MMCSDIO2
McBSP2
MPU/DSP dynamic shared
GPIO1, 2, 3, 4
32-kHz synchro counter
MPU public peripherals
USB controllers
32
µWire I/F
MPU private peripherals
Camera I/F
RTC
Timers (3)
PWT
Watchdog timer
PWL
Level 1/2 interrupt handlers
Keyboard I/F
Configuration registers
HDQ/1-Wire
System DMA
MMCSDIO1
RNG
MPUIO
SHA1/MD5
LPG1, 2
32-kHz watchdog
FAC
LCDCONV
OS timer
17