Texas Instruments OMAP5912 Reference Manual page 1667

McBSP Exception/Error Conditions
4.4.1 Example of the Underflow Condition
Figure 29. Underflow During McBSP Transmission
CLKX
FSX
A1
DX
Á
XRDY
XEMPTY_
4.4.2 Example of Preventing Underflow Condition
56 Multichannel Buffered Serial Ports (McBSPs)
Note:
If both DXRs are needed (word length larger than 16 bits), the CPU or the
DMA controller must load DXR2 first and then load DXR1. As soon as DXR1
is loaded, the contents of both DXRs are copied to the transmit shift registers
(XSRs). If DXR2 is not loaded first, the previous content of DXR2 is passed
to the XSR2.
XEMPTY is deactivated (XEMPTY = 1) when a new word in DXR1 is transferred
to XSR1. If FSXM = 1 in PCR and FSGM = 0 in SRGR2, the transmitter
generates a single internal FSX pulse in response to a DXR-to-XSR copy.
Otherwise, the transmitter waits for the next frame-synchronization pulse before
sending out the next frame on DX.
When the transmitter is taken out of reset (XRST = 1), it is in a transmitter
ready (XRDY = 1 in SPCR2) and transmitter empty (XEMPTY = 0) state. If
DXR1 is loaded by the CPU or the DMA controller before internal FSX goes
active high, a valid DXR-to-XSR transfer occurs. This allows for the first word
of the first frame to be valid even before the transmit frame-synchronization
pulse is generated
frame-synchronization pulse is detected before DXR1 is loaded, zeros are
output on DX.
Figure 29 shows an underflow condition. After B is transmitted, DXR1 is not
reloaded before the subsequent frame-synchronization pulse. Thus, B is
again transmitted on DX.
A0 B7 B6
Á
DXR1 to XSR1 copy(B)
Figure 30 shows the case of writing to DXR1 just before an underflow condition
would otherwise occur. After B is transmitted, C is written to DXR1 before the
next frame-synchronization pulse. As a result, there is no underflow; B is not
transmitted twice.
or detected. Alternatively,
B5 B4 B3 B2 B1 B0
Á Á
if a transmit
B7 B6 B5
Á Á
Write to DXR1(C)
SPRU762B