Texas Instruments OMAP5912 Reference Manual page 1658

3.5.2 Single-Rate ST-Bus Clock
Figure 21. Single-Rate Clock Example
CLKS
FSR external
Internal FSG, FSR,
internal FSX
Internal CLKG, CLKR,
internal CLKX
(first FSR)
DR, DX (first FSR)
Internal CLKG, CLKR,
(subsequent FSR)
DR, DX
(subsequent FSR)
3.5.3 Other Double-Rate Clock
SPRU762B
The example in Figure 21 is the same as the double-rate ST-bus clock
example in section 3.5.1 except that:
CLKGDV = 0: CLKS drives internal CLK(R/X) without any divide down
-
(single-rate clock).
CLKSP = 0: Rising edge of CLKS generates CLKG and internal
-
CLK(R/X).
Á Á
W1B7 W1B6
W32B0 W1B7 W1B6
The rising edge of CLKS is used to detect the external FSR pulse, which is used
to resynchronize internal McBSP clocks and generate a frame-synchronization
pulse for internal use. The internal frame-synchronization pulse is generated so
that it is wide enough to be detected on the falling edge of internal clocks.
The example in Figure 22 is the same as the double-rate ST-bus clock
example in section 3.5.1 except that:
CLKSP = 0: Rising edge of CLKS generates CLKG and thus CLK(R/X).
-
CLKGDV = 1: Frequency of CLKG (and thus internal CLKR and internal
-
CLKX) is half CLKS frequency.
FSRM/FSXM = 0: Frame synchronization is externally generated. The
-
frame-synchronization pulse is wide enough to be detected.
GSYNC = 0: CLKS drives CLKG. CLKG runs freely; it is not
-
resynchronized by a pulse on the FSR pin.
FSRP/FSXP = 0: Active-high input frame-synchronization signal.
-
RDATDLY/XDATDLY = 1: Data delay of one bit.
-
McBSP Sample Rate Generator
W1B5 W1B4 W1B3 W1B2
W1B5 W1B4 W1B3 W1B2
Multichannel Buffered Serial Ports (McBSPs)
W1B1 W1B0 W2B7
W1B1 W1B0 W2B7
WxBy = word x bit y
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