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Introduction to McBSPs
1.1
Key Features of the McBSPs
18
Multichannel Buffered Serial Ports (McBSPs)
The McBSPs feature:
Full-duplex communication
-
Double-buffered transmission and triple-buffered reception, which allow
-
a continuous data stream
Independent clocking and framing for reception and for transmission
-
The capability to send interrupts to the CPU and to send DMA events to
-
the DMA controller
128 channels for transmission and for reception
-
Multichannel selection modes that enable or disable block transfers in
-
each of the channels
Direct interface to industry-standard codecs, analog interface chips
-
(AICs), and other serially connected A/D and D/A devices
Support
for
external
-
frame-synchronization signals
A programmable sample rate generator for internal generation and control
-
of clock signals and frame-synchronization signals
Programmable polarity for frame-synchronization pulses and clock
-
signals
Direct interface to:
-
T1/E1 framers
J
Multivendor integration protocol (MVIP) switching compatible and
J
ST-BUS compliant devices including:
H
MVIP framers
H
H.100 framers
H
SCSA framers
IOM-2 compliant devices
J
I2S compliant devices
J
SPI devices
J
A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits
-
Note:
A value of the chosen data size is referred to as a serial word or word through-
out the McBSP documentation. Elsewhere, word is used to describe a 16-bit
value.
generation
of
clock
signals
and
SPRU762B
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